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		<title>10nm-class D1X DDR4 &#8211; Samsung Global Newsroom</title>
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            <title>10nm-class D1X DDR4 &#8211; Samsung Global Newsroom</title>
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				<title><![CDATA[Samsung Announces Industry’s First EUV DRAM with Shipment of First Million Modules]]></title>
				<link>https://news.samsung.com/global/samsung-announces-industrys-first-euv-dram-with-shipment-of-first-million-modules</link>
				<pubDate>Wed, 25 Mar 2020 08:00:42 +0000</pubDate>
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				<dc:creator><![CDATA[Samsung Newsroom]]></dc:creator>
						<category><![CDATA[Press Release]]></category>
		<category><![CDATA[Semiconductors]]></category>
		<category><![CDATA[10nm-class D1X DDR4]]></category>
		<category><![CDATA[EUV]]></category>
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									<description><![CDATA[Samsung Electronics, the world leader in advanced memory technology, today announced that it has successfully shipped one million of the industry’s first 10nm-class (D1x) DDR4 (Double Date Rate 4) DRAM modules based on extreme ultraviolet (EUV) technology. The new EUV-based DRAM modules have completed global customer evaluations, and will open the door to more cutting-edge […]]]></description>
																<content:encoded><![CDATA[<p>Samsung Electronics, the world leader in advanced memory technology, today announced that it has successfully shipped one million of the industry’s first <span>10nm-class (D1x) </span>DDR4 <span>(Double Date Rate 4) </span>DRAM modules based on extreme ultraviolet (EUV) technology. The new EUV-based DRAM modules have completed global customer evaluations, and will open the door to more cutting-edge EUV process nodes for use in premium PC, mobile, enterprise server and datacenter applications.</p>
<p>“With the production of our new <span>EUV-based DRAM</span>, we are demonstrating our full commitment toward <span>providing revolutionary DRAM solutions </span>in support of our global IT customers,” said Jung-bae Lee, executive vice president of DRAM Product & Technology at Samsung Electronics. “This major advancement underscores how we will continue contributing to global IT innovation through timely development of leading-edge process technologies and next-generation memory products for the premium memory market.”</p>
<p>Samsung is the first to adopt EUV in DRAM production to overcome <span>challenges in DRAM scaling. </span>EUV technology reduces repetitive steps in multi-patterning and improves patterning accuracy, enabling enhanced performance and greater yields as well as shortened development time.</p>
<p><span>EUV will be fully deployed in Samsung’s future generations of DRAM, starting with its </span>fourth-<span>generation 10nm-class (D1a) or the highly-advanced 14nm-class, DRAM. </span>Samsung expects to begin volume production of D1a-based DDR5 and LPDDR5 next year, which would double manufacturing productivity of the 12-inch D1x wafers.</p>
<p>In line with the expansion of the DDR5/LPDDR5 market next year, the company will further strengthen its collaboration with leading IT customers and semiconductor vendors on optimizing standard specifications, as it accelerates the transition to DDR5/LPDDR5 throughout the memory market.</p>
<p>To better address the growing demand for next-generation premium DRAM, Samsung will start the operation of a second semiconductor fabrication line in Pyeongtaek, South Korea, within the second half of this year.</p>
<h3><span style="color: #000080"><strong>Timeline of Samsung DRAM Milestones</strong></span></h3>
<table width="1000">
<tbody>
<tr>
<td style="text-align: center" width="300"><strong>Date</strong></td>
<td style="text-align: center" width="700"><strong>Samsung DRAM Milestones</strong></td>
</tr>
<tr>
<td style="text-align: center" width="141">2021 (TBD)</td>
<td style="text-align: center" width="384">4th-gen 10nm-class (1a) EUV-based 16Gb DDR5/LPDDR5 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">March 2020</td>
<td style="text-align: center" width="384">4th-gen 10nm-class (1a) EUV-based DRAM development</td>
</tr>
<tr>
<td style="text-align: center" width="141">September 2019</td>
<td style="text-align: center" width="384">3rd-gen 10nm-class (1z) 8Gb DDR4 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">June 2019</td>
<td style="text-align: center" width="384">2nd-gen 10nm-class (1y) 12Gb LPDDR5 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">March 2019</td>
<td style="text-align: center" width="384">3rd-gen 10nm-class (1z) 8Gb DDR4 development</td>
</tr>
<tr>
<td style="text-align: center" width="141">November 2017</td>
<td style="text-align: center" width="384">2nd-gen 10nm-class (1y) 8Gb DDR4 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">September 2016</td>
<td style="text-align: center" width="384">1st-gen 10nm-class (1x) 16Gb LPDDR4/4X mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">February 2016</td>
<td style="text-align: center" width="384">1st-gen 10nm-class (1x) 8Gb DDR4 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">October 2015</td>
<td style="text-align: center" width="384">20nm (2z) 12Gb LPDDR4 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">December 2014</td>
<td style="text-align: center" width="384">20nm (2z) 8Gb GDDR5 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">December 2014</td>
<td style="text-align: center" width="384">20nm (2z) 8Gb LPDDR4 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">October 2014</td>
<td style="text-align: center" width="384">20nm (2z) 8Gb DDR4 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">February 2014</td>
<td style="text-align: center" width="384">20nm (2z) 4Gb DDR3 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">February 2014</td>
<td style="text-align: center" width="384">20nm-class (2y) 8Gb LPDDR4 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">November 2013</td>
<td style="text-align: center" width="384">20nm-class (2y) 6Gb LPDDR3 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">November 2012</td>
<td style="text-align: center" width="384">20nm-class (2y) 4Gb DDR3 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">September 2011</td>
<td style="text-align: center" width="384">20nm-class (2x) 2Gb DDR3 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">July 2010</td>
<td style="text-align: center" width="384">30nm-class 2Gb DDR3 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">February 2010</td>
<td style="text-align: center" width="384">40nm-class 4Gb DDR3 mass production</td>
</tr>
<tr>
<td style="text-align: center" width="141">July 2009</td>
<td style="text-align: center" width="384">40nm-class 2Gb DDR3 mass production</td>
</tr>
</tbody>
</table>
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