By leveraging Samsung’s leading-edge foundry and advanced packaging products, Preferred Networks aims to develop powerful AI accelerators that meet the ever-growing demand for computing power driven by generative AI.

Since starting mass production of the industry’s first 3nm process node applying Gate-All-Around (GAA) transistor architecture, Samsung has strengthened its GAA technology leadership by successfully winning orders for the 2nm process with further upgrades in performance and power efficiency.

The cooperation with Preferred Networks marks the first achievement for Japanese companies in the field of large-sized heterogeneous integrated package technologies and Samsung plans to accelerate its leading global advanced package market offensive.¹

The 2.5D Advanced Package I-Cube S technology included in the turnkey solutions, is a heterogeneous integration package technology, with multiple chips in one package to enhance inter-connection speed and reduce package size. The use of the silicon interposer (Si-interposer) is crucial in achieving ultra-fine redistribution layer (RDL) and stabilizing power integrity for optimal semiconductor performance. GAONCHIPS, a specialized system semiconductor development company, designed the chip.

“We are excited to lead in AI accelerator technology with Samsung Electronics’ 2nm GAA process. This solution will significantly support Preferred Networks’ ongoing efforts to build highly energy-efficient, high-performance computing hardware that meets the ever-growing computing demands from generative AI technologies, especially large language models.,” said Junichiro Makino, VP and Chief Technology Officer (CTO) of Computing Architecture at Preferred Networks.

“This order is pivotal as it validates Samsung’s 2nm GAA process technology and Advanced Package technology as an ideal solution for next-generation AI accelerators,” said Taejoong Song, Corporate VP and the head of Foundry Business Development Team at Samsung Electronics. “We are committed to closely collaborating with our customers ensuring that the high performance and low power characteristics of our products are fully realized.”

Preferred Networks, headquartered in Tokyo, develops advanced software and hardware technologies by vertically integrating the AI value chain from chips to supercomputers and generative AI foundation models. It provides solutions and products for various industries such as manufacturing, transportation, healthcare, entertainment and education. The company is one of the major players in the global AI market, achieving first place three times in the past five years on the Green500² list of supercomputers.

Based on this collaboration, Samsung and Preferred Networks plan to showcase groundbreaking AI chiplet solutions for the next-generation data center and generative AI computing market in the future.³

¹ Heterogeneous integration packaging technology integrates different types of chips – such as memory, logic and sensors – in a single package.
² Green500: the ranking of the TOP500 supercomputers in the world based on their performance-per-watt efficiency
³ Chiplet Solution: A technology of assembling into a single package with other different chips performing different fuctions through the packaging technologies

The “Beyond Moore” Era: Pushing the Boundaries of Semiconductors

In the past, the technological advancement in the world of semiconductors revolved around who could make smaller transistors and fit more on a single chip. Gordon Moore predicted that the density of transistors on a chip doubles every 24 months — the famous “Moore’s Law”. Although it has gone through some adjustments over history to reflect the speed of technological growth, “Moore’s Law” has been considered the fundamental principle of semiconductor technology development for the last five decades.

Today’s era of smartphones, mobile internet, AI and big data calls for increasingly faster speeds of computing performance. However, the speed of semiconductor innovation and technology advancement has slowed down, and chip miniaturization has reached physical limits, which has caused the speed at which transistors are growing smaller to slow down. In other words, we are now falling behind Moore’s Law.

The market also demands semiconductors to be versatile, encompassing a variety of features such as analog or RF wireless communication in one chip. But as the semiconductor process becomes increasingly miniaturized, it gets increasingly difficult to maintain analog performance. It is indeed becoming difficult to address the needs of the market just through process miniaturization based on Moore’s Law.

In order to overcome these limitations of semiconductor technology, an approach that goes beyond the existing Moore’s Law is required, and we call this “Beyond Moore”.

“Advanced Package, Leading the Beyond Moore Era”

Our answer to the Beyond Moore era is Advanced Package technology. Through advanced Heterogeneous Integration, which connects multiple chips horizontally and vertically, more transistors can be planted on a single chip (or package) and offer performance that is more powerful than the sum of all parts.

According to market research, the CAGR of the advanced packaging industry is estimated at 9.6% growth rate between 2021 and 2027. In fact, 2.5D¹ and 3D packages² implementing heterogeneous integration is expected to show an even higher growth rate of 14%.

Governments are also paying close attention. The South Korean Ministry of Trade, Industry and Energy hosted a forum on semiconductor packaging technology in February, while DARPA (Defense Advanced Research Projects Agency) of the US Department of Defense announced the allocation of a large-scale budget for advanced package-related fields last April. The Japanese government also announced new incentives to attract research centers, as well as establishing a dedicated symposium.

“One-Stop Advanced Package Solution with High Performance and Low Power”

In a bid to address the growing importance of advanced packaging technology, Samsung Electronics established the AVP (AdVanced Package) Business Team under the Device Solutions Division last December to boost the company’s capabilities in advanced packaging technology and maximize the synergy between business units.

Samsung Electronics, with industry-leading expertise in memory, logic foundry and package business, is well-positioned to utilize heterogeneous integration to offer competitive 2.5D and 3D packages that connect state-of-the-art logic semiconductors produced with EUV and high-performance memory semiconductors such as HBM.

The AVP Business Team operates under a business model that provides one-stop advanced package solutions that enable high-performance and low-power solutions. We communicate closely and directly with customers in order to provide solutions tailored to the needs of each customer and product. Our focus areas are the development of next-generation 2.5D and 3D advanced package solutions based on RDL,³ Si Interposer/Bridge⁴ and TSV⁵ stacking technologies.

“Our Future Beyond Connection”

The goal of the AVP Business Team is “hyper-connection” (or “hyper-integration”). “Hyper-connection” is more than a simple sum of the performance and functions of each semiconductor. We envision creating a greater synergy that connects semiconductors to the world, connects people to people and connects customers’ imaginations to reality.

Samsung Electronics is committed to a competitive development and production strategy, with proprietary packaging technology compatible with the large-area trend. Based on customer-oriented business development that ensures prompt responses to customer requests, the AVP Business Team will bring products of imagination to reality.

¹ 2.5D package: A package which integrates a single-layer logic semiconductor and multi-layer memory semiconductor together on a substrate
² 3D package: a package in which multiple logic/memory semiconductors are vertically integrated
³ RDL (Redistribution Layer): Advanced packaging technology that places an extra metal layer in between a small and large circuit board to integrate the two
⁴ Si Interposer/Bridge: The microcircuit board inserted between the IC chip and PCB, which physically connects the chip and board by acting as the mid-level wiring
⁵ TSV (Through Silicon Via): Advanced package technology that grinds the surface of the chip, drills hundreds of microscopic holes and connects the electrodes that vertically penetrate the holes in the top and bottom chips.

“H-Cube solution, which is jointly developed with Samsung Electro-Mechanics (SEMCO) and Amkor Technology, is suited to high-performance semiconductors that need to integrate a large number of silicon dies,” said Moonsoo Kang, Senior Vice President and Head of Foundry Market Strategy Team at Samsung Electronics. “By expanding and enriching the foundry ecosystem, we will provide various package solutions to find a breakthrough in the challenges our customers are facing.”

“In today’s environment where system integration is increasingly required and substrate supplies are constrained, Samsung Foundry and Amkor Technology have successfully co-developed H-Cube to overcome these challenges,” said JinYoung Kim, Senior Vice President of Global R&D Center at Amkor Technology. “This development lowers barriers to entry in the HPC/AI market and demonstrates successful collaboration and partnership between the foundry and outsourced semiconductor assembly and test (OSAT) company.”

H-Cube Structure and Features

2.5D packaging enables logic chips or high-bandwidth memory (HBM) to be placed on top of a silicon interposer in a small form factor. Samsung’s H-Cube technology features a hybrid substrate combined with a fine-pitch substrate which is capable of fine bump connection, and a High-Density Interconnection (HDI) substrate, to implement large sizes into 2.5D packaging.

With the recent increase in specifications required in the HPC, AI and networking application market segments, large-area packaging is becoming important as the number and size of chips mounted in one package increases or high-bandwidth communication is required. For attachment and connection of silicon dies including the interposer, fine-pitch substrates are essential but prices rise significantly following an increase in size.

H-Cube Package Structure Concept

When integrating six or more HBMs, the difficulty in manufacturing the large-area substrate increases rapidly, resulting in decreased efficiency. Samsung solved this problem by applying a hybrid substrate structure in which HDI substrates that are easy to implement in large-area are overlapped under a high-end fine-pitch substrate.

By decreasing the pitch of solder ball, which electrically connects the chip and the substrate, by 35% compared to the conventional ball pitch, the size of fine-pitch substrate can be minimized, while adding HDI substrate (module PCB) under the fine-pitch substrate to secure connectivity with the system board.

In addition, to enhance the reliability of the H-Cube solution, Samsung applied its proprietary signal/power integrity analysis technology that can stably supply power while minimizing the signal loss or distortion when stacking multiple logic chips and HBMs.

Looking ahead, in cooperation with its ecosystem partners, Samsung will hold its 3^rd Annual ‘Samsung Advanced Foundry Ecosystem (SAFE) Forum’ virtually on November 17 (PST).

For pre-registration on the SAFE forum, please visit https://www.samsungfoundry.com.