The “Beyond Moore” Era: Pushing the Boundaries of Semiconductors

In the past, the technological advancement in the world of semiconductors revolved around who could make smaller transistors and fit more on a single chip. Gordon Moore predicted that the density of transistors on a chip doubles every 24 months — the famous “Moore’s Law”. Although it has gone through some adjustments over history to reflect the speed of technological growth, “Moore’s Law” has been considered the fundamental principle of semiconductor technology development for the last five decades.

Today’s era of smartphones, mobile internet, AI and big data calls for increasingly faster speeds of computing performance. However, the speed of semiconductor innovation and technology advancement has slowed down, and chip miniaturization has reached physical limits, which has caused the speed at which transistors are growing smaller to slow down. In other words, we are now falling behind Moore’s Law.

The market also demands semiconductors to be versatile, encompassing a variety of features such as analog or RF wireless communication in one chip. But as the semiconductor process becomes increasingly miniaturized, it gets increasingly difficult to maintain analog performance. It is indeed becoming difficult to address the needs of the market just through process miniaturization based on Moore’s Law.

In order to overcome these limitations of semiconductor technology, an approach that goes beyond the existing Moore’s Law is required, and we call this “Beyond Moore”.

“Advanced Package, Leading the Beyond Moore Era”

Our answer to the Beyond Moore era is Advanced Package technology. Through advanced Heterogeneous Integration, which connects multiple chips horizontally and vertically, more transistors can be planted on a single chip (or package) and offer performance that is more powerful than the sum of all parts.

According to market research, the CAGR of the advanced packaging industry is estimated at 9.6% growth rate between 2021 and 2027. In fact, 2.5D¹ and 3D packages² implementing heterogeneous integration is expected to show an even higher growth rate of 14%.

Governments are also paying close attention. The South Korean Ministry of Trade, Industry and Energy hosted a forum on semiconductor packaging technology in February, while DARPA (Defense Advanced Research Projects Agency) of the US Department of Defense announced the allocation of a large-scale budget for advanced package-related fields last April. The Japanese government also announced new incentives to attract research centers, as well as establishing a dedicated symposium.

“One-Stop Advanced Package Solution with High Performance and Low Power”

In a bid to address the growing importance of advanced packaging technology, Samsung Electronics established the AVP (AdVanced Package) Business Team under the Device Solutions Division last December to boost the company’s capabilities in advanced packaging technology and maximize the synergy between business units.

Samsung Electronics, with industry-leading expertise in memory, logic foundry and package business, is well-positioned to utilize heterogeneous integration to offer competitive 2.5D and 3D packages that connect state-of-the-art logic semiconductors produced with EUV and high-performance memory semiconductors such as HBM.

The AVP Business Team operates under a business model that provides one-stop advanced package solutions that enable high-performance and low-power solutions. We communicate closely and directly with customers in order to provide solutions tailored to the needs of each customer and product. Our focus areas are the development of next-generation 2.5D and 3D advanced package solutions based on RDL,³ Si Interposer/Bridge⁴ and TSV⁵ stacking technologies.

“Our Future Beyond Connection”

The goal of the AVP Business Team is “hyper-connection” (or “hyper-integration”). “Hyper-connection” is more than a simple sum of the performance and functions of each semiconductor. We envision creating a greater synergy that connects semiconductors to the world, connects people to people and connects customers’ imaginations to reality.

Samsung Electronics is committed to a competitive development and production strategy, with proprietary packaging technology compatible with the large-area trend. Based on customer-oriented business development that ensures prompt responses to customer requests, the AVP Business Team will bring products of imagination to reality.

¹ 2.5D package: A package which integrates a single-layer logic semiconductor and multi-layer memory semiconductor together on a substrate
² 3D package: a package in which multiple logic/memory semiconductors are vertically integrated
³ RDL (Redistribution Layer): Advanced packaging technology that places an extra metal layer in between a small and large circuit board to integrate the two
⁴ Si Interposer/Bridge: The microcircuit board inserted between the IC chip and PCB, which physically connects the chip and board by acting as the mid-level wiring
⁵ TSV (Through Silicon Via): Advanced package technology that grinds the surface of the chip, drills hundreds of microscopic holes and connects the electrodes that vertically penetrate the holes in the top and bottom chips.

Samsung’s new innovation is considered one of the most challenging packaging technologies for mass production of high-performance chips, as it requires pinpoint accuracy to vertically interconnect 12 DRAM chips through a three-dimensional configuration of more than 60,000 TSV holes, each of which is one-twentieth the thickness of a single strand of human hair.

The thickness of the package (720㎛) remains the same as current 8-layer High Bandwidth Memory-2 (HBM2) products, which is a substantial advancement in component design. This will help customers release next-generation, high-capacity products with higher performance capacity without having to change their system configuration designs.

In addition, the 3D packaging technology also features a shorter data transmission time between chips than the currently existing wire bonding technology, resulting in significantly faster speed and lower power consumption.

“Packaging technology that secures all of the intricacies of ultra-performance memory is becoming tremendously important, with the wide variety of new-age applications, such as artificial intelligence (AI) and High Power Computing (HPC),” said Hong-Joo Baek, executive vice president of TSP (Test & System Package) at Samsung Electronics.

“As Moore’s law scaling reaches its limit, the role of 3D-TSV technology is expected to become even more critical. We want to be at the forefront of this state-of-the-art chip packaging technology.”

Relying on its 12-layer 3D-TSV technology, Samsung will offer the highest DRAM performance for applications that are data-intensive and extremely high-speed.

Also, by increasing the number of stacked layers from eight to 12, Samsung will soon be able to mass produce 24-gigabyte (GB)* High Bandwidth Memory, which provides three times the capacity of 8GB high bandwidth memory on the market today.

Samsung will be able to meet the rapidly growing market demand for high-capacity HBM solutions with its cutting-edge 12-layer 3D TSV technology and it hopes to solidify its leadership in the premium semiconductor market.

*8GB mass-production product= 8Gb x 8 layers, 24GB developed product= 16Gb x 12 layers

*PKG cross section structure

*Wire bonding vs TSV technology