Samsung Electronics today announced the development of its 16-gigabit (Gb) DDR5 DRAM built using the industry’s first 12-nanometer (nm)-class process technology, as well as the completion of product evaluation for compatibility with AMD.

“Our 12nm-range DRAM will be a key enabler in driving market-wide adoption of DDR5 DRAM,” said Jooyoung Lee, Executive Vice President of DRAM Product & Technology at Samsung Electronics. “With exceptional performance and power efficiency, we expect our new DRAM to serve as the foundation for more sustainable operations in areas such as next-generation computing, data centers and AI-driven systems.”

“Innovation often requires close collaboration with industry partners to push the bounds of technology,” said Joe Macri, Senior VP, Corporate Fellow and Client, Compute and Graphics CTO at AMD. “We are thrilled to once again collaborate with Samsung, particularly on introducing DDR5 memory products that are optimized and validated on ‘Zen’ platforms.”

This technological leap was made possible through the use of a new high-κ material that increases cell capacitance and proprietary design technology that improves critical circuit characteristics. Combined with advanced, multi-layer extreme ultraviolet (EUV) lithography, the new DRAM features the industry’s highest die density, which enables a 20 percent gain in wafer productivity.

Leveraging the latest DDR5 standard, Samsung’s 12nm-class DRAM will help unlock speeds of up to 7.2 gigabits per second (Gbps). This translates into processing two 30 gigabyte (GB) UHD movies in just one second.

The new DRAM’s exceptional speed is matched by greater power efficiency. Consuming up to 23 percent less power than the previous DRAM, the 12nm-class DRAM will be an ideal solution for global IT companies pursuing more environment-friendly operations.

With mass production set to begin in 2023, Samsung plans to broaden its DRAM lineup built on this cutting-edge 12nm-class process technology into a wide range of market segments as it continues to work with industry partners to support the rapid expansion of next-generation computing.

Future-First Memory Solutions for Data-Driven Innovation

With the development of their DDR5 solution, Samsung, a company known for changing the landscape of the global dynamic random access memory (DRAM) market, has introduced yet another generational shift in the IT industry. Furthermore, following the release earlier this year of CPUs that support DDR5, tremendous change is expected in the computing landscape, too, with growth expected to encompass gaming and mainstream PCs as well.

Compared to its predecessor which hit the market in 2013, DDR4, DDR5 DRAM boasts twice the speed and four times the capacity, at 4800Mpbs and 512GB respectively.¹ This next-generation high-performance memory allows networks to handle the soaring amounts of data generated by cloud computing, AI and autonomous driving systems. Unlike DDR4, DDR5 directly incorporates a power management integrated circuit (PMIC) into a dual in-line memory module (DIMM), resulting in a 30 percent increase in power efficiency on the module level and a more stable power supply.

Data centers are the main users of DDR5, since, in order to work at their full potential, they require low-power, high-performance memory as they consume large amounts of energy to perform operations and keep servers cool. Starting from the third quarter of this year, existing DRAMs for servers are set to steadily be replaced by DDR5, a shift that could help data centers stay cost-efficient and encourage sustainable, eco-friendly development.

Going beyond the performance limitations of existing DRAMs, DDR5 will be pivotal in leading data-driven innovation in terms of speed, capacity and eco-friendliness. In order to learn more about the new world DDR5 is helping to build, take a look at the video below.

¹ These figures concern modules for servers.

Samsung Electronics, the world leader in advanced memory technology, today announced that it has begun mass producing the industry’s smallest, 14-nanometer (nm), DRAM based on extreme ultraviolet (EUV) technology. Following the company’s shipment of the industry-first EUV DRAM in March of last year, Samsung has increased the number of EUV layers to five to deliver today’s finest, most advanced DRAM process for its DDR5 solutions.

“We have led the DRAM market for nearly three decades by pioneering key patterning technology innovations,” said Jooyoung Lee, Senior Vice President and Head of DRAM Product & Technology at Samsung Electronics. “Today, Samsung is setting another technology milestone with multi-layer EUV that has enabled extreme miniaturization at 14nm — a feat not possible with the conventional argon fluoride (ArF) process. Building on this advancement, we will continue to provide the most differentiated memory solutions by fully addressing the need for greater performance and capacity in the data-driven world of 5G, AI and the metaverse.”

As DRAM continues to scale down the 10nm-range, EUV technology becomes increasingly important to improve patterning accuracy for higher performance and greater yields. By applying five EUV layers to its 14nm DRAM, Samsung has achieved the highest bit density while enhancing the overall wafer productivity by approximately 20%. Additionally, the 14nm process can help bring down power consumption by nearly 20% compared to the previous-generation DRAM node.

Leveraging the latest DDR5 standard, Samsung’s 14nm DRAM will help unlock unprecedented speeds of up to 7.2 gigabits per second (Gbps), which is more than twice the DDR4 speed of up to 3.2Gbps.

Samsung plans to expand its 14nm DDR5 portfolio to support data center, supercomputer and enterprise server applications. Also, Samsung expects to grow its 14nm DRAM chip density to 24Gb in better meeting the rapidly-growing data demands of global IT systems.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced the industry’s first integrated power management ICs (PMICs) — S2FPD01, S2FPD02 and S2FPC01, for the fifth-generation double data rate (DDR5) dual in-line memory module (DIMM).

One major design improvement to the newest generation DRAM solution involves integrating the PMIC into the memory module — previous generations placed the PMIC on the motherboard — offering increased compatibility and signal integrity, and providing a more reliable and sustained performance.

For improved performance efficiency and load-transient responses, Samsung’s new PMICs for DDR5 modules have been equipped with a high-efficiency hybrid gate driver and a proprietary control design (asynchronous-based dual-phase buck control scheme).

This scheme allows the DC voltage to step down from high to low with a fast transient response to changes in the output load current and adapts the conversion accordingly to efficiently regulate its output voltage at near-constant levels. The control scheme also features both pulse width and pulse frequency modulation methods, preventing delays and malfunctions when switching modes.

“With enhanced power efficiency and low output ripple voltage, the new PMICs S2FPD01, S2FPD02 and S2FPC01 allow data centers, enterprise servers and PC applications to take full advantage of their DDR5 performance for highly demanding, memory-intensive tasks,” said Harry Cho, vice president of System LSI marketing at Samsung Electronics.

Two of Samsung’s new DDR5 DIMM PMIC solutions, the S2FPD01 and the S2FPD02, offer optimal performance for today’s data center and enterprise servers that must run heavy analytics, machine and deep learning, and other various computing tasks in real time. The FPD01 is designed for modules with low density; FPD02 for higher density.

In addition, by implementing a high-efficiency hybrid gate driver instead of a linear regulator, Samsung’s new PMICs can operate at up to 91-percent power efficiency.

The S2FPC01, Samsung’s other new PMIC, is tailored for use in desktop or laptop PCs. Designed on a 90-nanometer (nm) process node, the PMIC solution offers a more agile performance in a smaller package.

Samsung’s DDR5 DIMM power management ICs, the S2FPD01, S2FPD02 and S2FPC01, are currently being sampled to customers.

Samsung Electronics, the world leader in advanced memory technology, today unveiled the industry’s first memory module supporting the new Compute Express Link (CXL) interconnect standard. Integrated with Samsung’s Double Data Rate 5 (DDR5) technology, this CXL-based module will enable server systems to significantly scale memory capacity and bandwidth, accelerating artificial intelligence (AI) and high-performance computing (HPC) workloads in data centers.

The rise of AI and big data has been fueling the trend toward heterogeneous computing, where multiple processors work in parallel to process massive volumes of data. CXL—an open, industry-supported interconnect based on the PCI Express (PCIe) 5.0 interface—enables high-speed, low latency communication between the host processor and devices such as accelerators, memory buffers and smart I/O devices, while expanding memory capacity and bandwidth well beyond what is possible today. Samsung has been collaborating with several data center, server and chipset manufacturers to develop next-generation interface technology since the CXL consortium was formed in 2019.

“This is the industry’s first DRAM-based memory solution that runs on the CXL interface, which will play a critical role in serving data-intensive applications including AI and machine learning in data centers as well as cloud environments,” said Cheolmin Park, vice president of the Memory Product Planning Team at Samsung Electronics. “Samsung will continue to raise the bar with memory interface innovation and capacity scaling to help our customers, and the industry at-large, better manage the demands of larger, more complex, real-time workloads that are key to AI and the data centers of tomorrow.”

Dr. Debendra Das Sharma, Intel Fellow and Director of I/O Technology and Standards at Intel said, “Data center architecture is rapidly evolving to support the growing demand and workloads for AI and ML, and CXL memory is expected to expand the use of memory to a new level. We continue to work with industry companies such as Samsung to develop a robust memory ecosystem around CXL.”

Dan McNamara, senior vice president and general manager, Server Business Unit, AMD, added, “AMD is committed to driving the next generation of performance in cloud and enterprise computing. Memory research is a critical piece to unlocking this performance, and we are excited to work with Samsung to deliver advanced interconnect technology to our data center customers.”

Unlike conventional DDR-based memory, which has limited memory channels, Samsung’s CXL-enabled DDR5 module can scale memory capacity to the terabyte level, while dramatically reducing system latency caused by memory caching.

In addition to CXL hardware innovation, Samsung has incorporated several controller and software technologies like memory mapping, interface converting and error management, which will allow CPUs or GPUs to recognize the CXL-based memory and utilize it as the main memory.

Samsung’s new module has been successfully validated on next-generation server platforms from Intel, signaling the beginning of an era for high-bandwidth, low latency CXL-based memory using the latest DDR5 standard. Samsung is also working with data center and cloud providers around the world to better accommodate the need for greater memory capacity that will be essential in handling big data applications including in-memory database systems.

As the DDR5-based CXL memory module becomes commercialized, Samsung intends to lead the industry in meeting the demand for next-generation high-performance computing technologies that rely on expanded memory capacity and bandwidth.

“Samsung is the only semiconductor company with logic and memory capabilities and the expertise to incorporate HKMG cutting-edge logic technology into memory product development,” said Young-Soo Sohn, Vice President of the DRAM Memory Planning/Enabling Group at Samsung Electronics. “By bringing this type of process innovation to DRAM manufacturing, we are able to offer our customers high-performance, yet energy-efficient memory solutions to power the computers needed for medical research, financial markets, autonomous driving, smart cities and beyond.”

“As the amount of data to be moved, stored and processed increases exponentially, the transition to DDR5 comes at a critical inflection point for cloud datacenters, networks and edge deployments,” said Carolyn Duran, Vice President and GM of Memory and IO Technology at Intel. “Intel’s engineering teams closely partner with memory leaders like Samsung to deliver fast, power-efficient DDR5 memory that is performance-optimized and compatible with our upcoming Intel Xeon Scalable processors, code-named Sapphire Rapids.”

Samsung’s DDR5 will utilize highly advanced HKMG technology that has been traditionally used in logic semiconductors. With continued scaling down of DRAM structures, the insulation layer has thinned, leading to a higher leakage current. By replacing the insulator with HKMG material, Samsung’s DDR5 will be able to reduce the leakage and reach new heights in performance. This new memory will also use approximately 13% less power, making it especially suitable for datacenters where energy efficiency is becoming increasingly critical.

The HKMG process was adopted in Samsung’s GDDR6 memory in 2018 for the first time in the industry. By expanding its use in DDR5, Samsung is further solidifying its leadership in next-generation DRAM technology.

Leveraging through-silicon via (TSV) technology, Samsung’s DDR5 stacks eight layers of 16Gb DRAM chips to offer the largest capacity of 512GB. TSV was first utilized in DRAM in 2014 when Samsung introduced server modules with capacities up to 256GB.

Samsung is currently sampling different variations of its DDR5 memory product family to customers for verification and, ultimately, certification with their leading-edge products to accelerate AI/ML, exascale computing, analytics, networking, and other data-intensive workloads.

“By developing innovative technologies in DRAM circuit design and process, we have broken through what has been a major barrier for DRAM scalability,” said Gyoyoung Jin, president of Memory Business at Samsung Electronics. “Through a rapid ramp-up of the 2nd-generation 10nm-class DRAM, we will expand our overall 10nm-class DRAM production more aggressively, in order to accommodate strong market demand and continue to strengthen our business competitiveness.”

Samsung’s 2nd-generation 10nm-class 8Gb DDR4 features an approximate 30 percent productivity gain over the company’s 1st–generation 10nm-class 8Gb DDR4. In addition, the new 8Gb DDR4’s performance levels and energy efficiency have been improved about 10 and 15 percent respectively, thanks to the use of an advanced, proprietary circuit design technology. The new 8Gb DDR4 can operate at 3,600 megabits per second (Mbps) per pin, compared to 3,200 Mbps of the company’s 1x-nm 8Gb DDR4.

To enable these achievements, Samsung has applied new technologies, without the use of an EUV process. The innovation here includes use of a high-sensitivity cell data sensing system and a progressive “air spacer” scheme.

In the cells of Samsung’s 2nd-generation 10nm-class DRAM, a newly devised data sensing system enables a more accurate determination of the data stored in each cell, which leads to a significant increase in the level of circuit integration and manufacturing productivity.

The new 10nm-class DRAM also makes use of a unique air spacer that has been placed around its bit lines to dramatically decrease parasitic capacitance**. Use of the air spacer enables not only a higher level of scaling, but also rapid cell operation.

With these advancements, Samsung is now accelerating its plans for much faster introductions of next-generation DRAM chips and systems, including DDR5, HBM3, LPDDR5 and GDDR6, for use in enterprise servers, mobile devices, supercomputers, HPC systems and high-speed graphics cards.

Samsung has finished validating its 2nd-generation 10nm-class DDR4 modules with CPU manufacturers, and next plans to work closely with its global IT customers in the development of more efficient next-generation computing systems.

In addition, the world’s leading DRAM producer expects to not only rapidly increase the production volume of the 2nd-generation 10nm-class DRAM lineups, but also to manufacture more of its mainstream 1st-generation 10nm-class DRAM, which together will meet the growing demands for DRAM in premium electronic systems worldwide.

* Editors’ Note 1: 10nm-class denotes a process technology node somewhere between 10 and 19 nanometers. Samsung launched its first DRAM product based on a 10nm-class process in February, 2016.

** Editors’ Note 2: Parasitic capacitance is unwanted capacitance that exists between the parts of an electronic circuit or electronic part, because of their proximity to each other. When two electrical conductors at different voltages are too close together, they are adversely affected by each other’s electric field and store opposite electric charges such as those produced by a capacitor.