Samsung Electronics, a world leader in advanced semiconductor technology, today unveiled plans for continuous process technology migration to 3- and 2-nanometer (nm) based on the company’s Gate-All-Around (GAA) transistor structure at its 5^th annual Samsung Foundry Forum (SFF) 2021.

With a theme of Adding One More Dimension, the multi-day virtual event is expected to draw over 2,000 global customers and partners. At this year’s event, Samsung will share its vision to bolster its leadership in the rapidly evolving foundry market by taking each respective part of foundry business to the next level: process technology, manufacturing operations and foundry services.

“We will increase our overall production capacity and lead the most advanced technologies while taking silicon scaling a step further and continuing technological innovation by application,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics.” Amid further digitalization prompted by the COVID-19 pandemic, our customers and partners will discover the limitless potential of silicon implementation for delivering the right technology at the right time.”

GAA Is Ready for Customers’ Adoption – 3nm MP in 2022, 2nm in 2025

With its enhanced power, performance and flexible design capability, Samsung’s unique GAA technology, Multi-Bridge-Channel FET (MBCFET^TM), is essential for continuing process migration. Samsung’s first 3nm GAA process node utilizing MBCFET will allow up to 35 percent decrease in area, 30 percent higher performance or 50 percent lower power consumption compared to the 5nm process. In addition to power, performance and area (PPA) improvements, as its process maturity has increased, 3nm’s logic yield is approaching a similar level to the 4nm process, which is currently in mass production.

Samsung is scheduled to start producing its customers’ first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023. Newly added to Samsung’s technology roadmap, the 2nm process node with MBCFET is in the early stages of development with mass production in 2025.

FinFET for CIS, DDI, MCU – 17nm Specialty Process Technology Debuts

Samsung Foundry is continuously improving its FinFET process technology to support specialty products with cost-effective and application-specific competitiveness. A good example of this is the company’s 17nm FinFET process node. In addition to the intrinsic benefits afforded by FinFET, the process node has excellent performance and power efficiency leveraging a 3D transistor architecture. Consequently, Samsung’s 17nm FinFET provides up to 43 percent decrease in area, 39 percent higher performance or a 49 percent increase in power efficiency compared to the 28nm process.

Additionally, Samsung is advancing its 14nm process in order to support 3.3V high voltage or flash-type embedded MRAM (eMRAM) which enables increased write speed and density. It will be a great option for applications such as micro controller units (MCUs), IoT and wearables. Samsung’s 8nm radio frequency (RF) platform is expected to expand the company’s leadership in the 5G semiconductor market from sub-6GHz to mmWave applications.

Looking ahead, in cooperation with its ecosystem partners, Samsung Foundry’s SAFE Forum will be held virtually in November 2021.

Compared to 7nm, Samsung’s 5nm FinFET process technology provides up to a 25 percent increase in logic area efficiency with 20 percent lower power consumption or 10 percent higher performance as a result of process improvement to enable us to have more innovative standard cell architecture.

In addition to power performance area (PPA) improvements from 7nm to 5nm, customers can fully leverage Samsung’s highly sophisticated EUV technology. Like its predecessor, 5nm uses EUV lithography in metal layer patterning and reduces mask layers while providing better fidelity.

Another key benefit of 5nm is that we can reuse all the 7nm intellectual property (IP) to 5nm. Thereby 7nm customers’ transitioning to 5nm will greatly benefit from reduced migration costs, pre-verified design ecosystem, and consequently shorten their 5nm product development.

As a result of the close collaboration between Samsung Foundry and its ‘Samsung Advanced Foundry Ecosystem (SAFE)’ partners, a robust design infrastructure for Samsung’s 5nm, including the process design kit (PDK), design methodologies (DM), electronic design automation (EDA) tools, and IP, has been provided since the fourth quarter of 2018. Besides, Samsung Foundry has already started offering 5nm Multi Project Wafer (MPW) service to customers.

“In successful completion of our 5nm development, we’ve proven our capabilities in EUV-based nodes,” said Charlie Bae, Executive Vice President of Foundry Business at Samsung Electronics. “In response to customers’ surging demand for advanced process technologies to differentiate their next-generation products, we continue our commitment to accelerating the volume production of EUV-based technologies.”

In October 2018, Samsung announced the readiness and its initial production of 7nm process, its first process node with EUV lithography technology. The company has provided commercial samples of the industry’s first EUV-based new products and has started mass production of 7nm process early this year.

Also, Samsung is collaborating with customers on 6nm, a customized EUV-based process node, and has already received the product tape-out of its first 6nm chip.

Mr. Bae continued, “Considering the various benefits including PPA and IP, Samsung’s EUV-based advanced nodes are expected to be in high demand for new and innovative applications such as 5G, artificial intelligence (AI), high performance computing (HPC), and automotive. Leveraging our robust technology competitiveness including our leadership in EUV lithography, Samsung will continue to deliver the most advanced technologies and solutions to customers.”

Samsung foundry’s EUV-based process technologies are currently being manufactured at the S3-line in Hwaseong, Korea. Additionally, Samsung will expand its EUV capacity to a new EUV line in Hwaseong, which is expected to be completed within the second half of 2019 and start production ramp-up from next year.

Based on Samsung Foundry’s 7LPP (7nm Low Power Plus) and 5LPE (5nm Low Power Early) process technologies, the Arm® Artisan® physical IP platform will enable 3GHz+ computing performance for Arm’s Cortex®-A76 processor.

Samsung’s 7LPP process technology will be ready for its initial production in the second half of 2018. The first extreme ultra violet (EUV) lithography process technology, and its key IPs, are in development and expected to be completed by the first half of 2019. Samsung’s 5LPE technology will allow greater area scaling and ultra-low power benefits due to the latest innovations in 7LPP process technology.

The Arm Artisan physical IP platform for Samsung’s 7LPP and 5LPE includes HD logic architecture, a comprehensive suite of memory compilers, and 1.8V and 3.3V GPIO libraries. In addition, for Samsung’s 7LPP and 5LPE process technologies, Arm will provide Artisan POP IP solutions on its latest processor cores featuring Arm DynamIQ technology. Arm’s POP IP solution is a core-hardening acceleration technology to enable the best Arm processor implementations and the most rapid time-to-market.

“Building an extensive and differentiated design ecosystem is a must for our foundry customers,” said Ryan Sanghyun Lee, vice president of Foundry Marketing Team at Samsung Electronics. “Collaboration with Arm in the fields of IP solutions is crucial to increase high-performance computing power and accelerate the growth of Artificial Intelligence (AI) and Machine Learning capabilities.”

“Arm and Samsung Foundry have collaborated on a large number of chips using Artisan physical IP on Samsung Foundry process technologies,” said Kelvin Low, vice president of marketing, Physical Design Group at Arm. “Samsung Foundry’s 7LPP and 5LPE nodes are innovative process technologies which will meet our mutual customers’ needs to deliver the next generation of advanced system-on-chips (SoCs) from mobile to hyperscale datacenters.”

Details of the recent updates to Samsung’s Foundry roadmap, from 7nm EUV development to 3GAAE (3nm Gate-All-Around Early) technology, and top-notch design enablement solutions were presented at Samsung Foundry Forum 2018 Korea on July 5, 2018, in Seoul. Samsung Foundry Forums were held in the United States and China earlier this year, sharing Samsung’s cutting-edge process technologies with global customers and partners.

For more information about Samsung Foundry, please visit www.samsungfoundry.com.

With comprehensive process technology roadmap updates down to 3-nanometer (nm) at the annual ‘Samsung Foundry Forum (SFF) 2018 USA’, Samsung Foundry is focused on providing customers with the tools necessary to design and manufacture powerful, yet energy-efficient system-on-chips (SoC) for a wide range of applications.

“The trend toward a smarter, connected world has the industry demanding more from silicon providers,” said Charlie Bae, executive vice president and head of the Foundry Sales & Marketing Team at Samsung Electronics. “To meet that demand, Samsung Foundry is powering innovation at the silicon level that will ultimately give people access to data, analysis, and insight in new and previously unthought-of ways to make human lives better. It is imperative for us to accomplish the first-time silicon success for our customers’ next-generation chip designs.”

Process Technology Roadmap Updates

• 7LPP (7nm Low Power Plus): 7LPP, the first semiconductor process technology to use an EUV lithography solution, is scheduled to be ready for production in the second half of this year. Key IPs are under development, aiming to be completed by the first half of 2019.

• 5LPE (5nm Low Power Early): Through further smart innovation from the 7LPP process, 5LPE will allow greater area scaling and ultra-low power benefits.

• 4LPE/LPP (4nm Low Power Early/Plus): The use of highly mature and verified FinFET technology will be extended to the 4nm process. As the last generation of FinFET, 4nm provides a smaller cell size, improved performance, and faster ramp-up to the stable level of yield by adopting proven 5LPE, supporting easy migration.

• 3GAAE/GAAP (3nm Gate-All-Around Early/Plus): 3nm process nodes adopt GAA, the next-generation device architecture. To overcome the physical scaling and performance limitations of the FinFET architecture, Samsung is developing its unique GAA technology, MBCFET^TM (Multi-Bridge-Channel FET) that uses a nano-sheet device. By enhancing the gate control, the performance of 3nm nodes will be significantly improved.

HPC (High-Performance Computing) Solutions

Samsung Foundry delivers the technology solutions to drive the latest hyper-scale datacenters and accelerate the growth of Artificial Intelligence (AI) and Machine Learning capability. From the latest 7LPP technology and beyond with its EUV capability, to the differentiated high-speed IPs such as 100Gbps+ SerDes on top of the innovative 2.5D/3D heterogeneous packaging, Samsung delivers the total platform solutions to greatly increase computing power and accelerate AI revolution.

Connected Device Solutions

From low-power microcontroller units (MCU) and next-generation connected devices to the most sophisticated autonomous vehicles based on 5G and Vehicle to Everything (V2X) communication, Samsung Foundry offers full-featured turnkey platforms to enable compelling products. A broad technology portfolio from 28/18 FD-SOI with eMRAM and RF capability to advanced 10/8nm FinFET processes will enable a great end-user experience for connected devices.

Mr. Bae continued, “Over the past year, we have focused on strengthening our EUV process portfolio to provide each of our customers with the finest technologies. Applying GAA structure to our next generation process node will enable us to take the lead in opening a new smart, connected world, while also to reinforcing our technology leadership.”

Details regarding Samsung Foundry can be found at www.samsungfoundry.com and www.linkedin.com/company/samsungfoundry.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced that it has begun mass production of the Exynos 7 Dual 7270. It is the first mobile application processor (AP) in the industry designed specifically for wearable devices with 14-nanometer (nm) FinFET process technology. It is also the first in its class to feature full connectivity and LTE modem integration.

Since 2015, Samsung has been leading the industry in expanding the adoption of 14nm technology for a wide variety of products from premium smartphones to entry-level mobile devices. With the Exynos 7270, the company also introduces the benefits of this cutting-edge technology to wearables.

“The Exynos 7270 presents a new paradigm for system-on-chips (SoC) dedicated to wearables,” said Ben K. Hur, Vice President of System LSI Marketing at Samsung Electronics. “Designed on our state-of-the-art process technology, this AP offers great power savings, 4G LTE modem and full connectivity solution integration, as well as innovative packaging technology optimized for wearable devices. It is a ground-breaking solution that will greatly accelerate wider adoption of wearable devices by overcoming limitations in current solutions such as energy usage and design flexibility.”

Powered by two Cortex^®-A53 cores, the Exynos 7270 makes full use of the 14nm process, delivering 20 percent improvement in power efficiency when compared to its predecessor built on 28nm, and thus notably extending the battery life. By integrating Cat.4 LTE modem, the new AP allows wearables to connect to a cellular service as a stand-alone device. Tethering and data transfer between devices is also possible with its embedded WiFi and Bluetooth connectivity. In addition, integrated connectivity capabilities support FM (frequency modulation) radio, and location-based services with GNSS (global navigation satellite system) solutions.

As well as the implementation of the advanced 14nm FinFET process, Samsung’s innovative packaging technology, SiP(system-in-package)-ePoP(embedded package-on-package), enables the Exynos 7270 to feature outstanding performance and energy-efficiency within a compact solution optimized for wearable devices. The technology combines the AP, DRAM and NAND flash memory chips as well as the PMIC (power management IC) together into a single package. The solution can offer more features than its predecessor in the same 100-square-millimeter (mm²) area while reducing the height by approximately 30 percent. This gives more room for device manufacturers to design high performance, ultra-slim wearable devices.

To expedite the development process, a reference platform comprised of the Exynos 7270, NFC (near field communication) and various sensors is currently available for device manufacturers and customers.

For more information about Samsung’s Exynos products, please visit www.samsung.com/exynos