As a state-of-the-art facility, NRD-K broke ground in 2022 and is set to become a key research base for Samsung’s memory, system LSI and foundry semiconductor R&D. With its advanced infrastructure, research and product-level verification will be able to take place under one roof. Samsung plans to invest about KRW 20 trillion by 2030 for the complex in an area covering about 109,000 square meters (m²) within its Giheung campus. The complex will also include an R&D-dedicated line scheduled to begin operation in mid-2025.

▲ Young Hyun Jun, Vice Chairman and Head of the Device Solutions Division at Samsung Electronics, gives a speech at the tool-in ceremony for Samsung’s new semiconductor research and development complex (NRD-K) in Giheung, Korea.

“NRD-K will bolster our development speed, enabling the company to create a virtuous cycle to accelerate fundamental research on next-generation technology and mass production. We will lay the foundation for a new leap forward in Giheung, where Samsung Electronics’ 50-year history of semiconductors began, and create a new future for the next 100 years,” said Young Hyun Jun, Vice Chairman and Head of the Device Solutions Division at Samsung Electronics.

“At a time when the importance of win-win partnerships is greater than ever, Applied Materials is committed to accelerating innovation velocity through deep collaboration with Samsung Electronics, working together to drive a new wave of growth for the semiconductor industry,” said Park Gwang-Sun, Head of Applied Materials Korea.

▲ Samsung Electronics Vice Chairman Young Hyun Jun, center, poses for a photo with executives during a tool-in ceremony at the Giheung Campus. * (left) Wanwoo Choi Head of People Team, Taeyang Yoon Chief Safety Officer, Jiwoon Im NRD-K P/J group head, Siyoung Choi Head of Foundry Business, BongHyun Kim DRAM Process Development Team, Jung-Bae Lee head of Memory Business, r, Young Hyun Jun, Vice Chairman and Head of the Device Solutions Division, Yong In Park Head of System LSI Business, Yujin Lee Flash Process Development Team, Seok Woo Nam Corporate President in charge / FAB Engineering & Operations, Jaihyuk Song Device Solutions CTO, HongGyeong Kim Head of Corporate Office.

Samsung’s Giheung campus, located south of Seoul, is the birthplace of the world’s first 64-megabit (Mb) DRAM in 1992, marking the beginning of the company’s semiconductor leadership. The establishment of the new R&D facility will usher in the latest developments in process technology and manufacturing tools, extending the site’s legacy at the forefront of innovation.

▲ Samsung Electronics executives poses for a photo during a tool-in ceremony at the Giheung Campus.

NRD-K will be set up with High NA extreme ultra-violet (EUV) lithography and new material deposition equipment aimed at accelerating the development of next-generation memory semiconductors such as 3D DRAM and V-NAND with more than 1,000 layers. In addition, wafer bonding infrastructure with innovative wafer-to-wafer bonding capabilities is also planned to dock.

Samsung invested a record KRW 8.87 trillion in R&D in the third quarter of this year, and continues to push boundaries to secure competitiveness in future technologies, such as advanced packaging for high bandwidth memory (HBM) production.

Samsung Electronics, a world leader in advanced memory technology, today announced that it has developed HBM3E 12H, the industry’s first 12-stack HBM3E DRAM and the highest-capacity HBM product to date.

Samsung’s HBM3E 12H provides an all-time high bandwidth of up to 1,280 gigabytes per second (GB/s) and an industry-leading capacity of 36 gigabytes (GB). In comparison to the 8-stack HBM3 8H, both aspects have improved by more than 50%.

“The industry’s AI service providers are increasingly requiring HBM with higher capacity, and our new HBM3E 12H product has been designed to answer that need,” said Yongcheol Bae, Executive Vice President of Memory Product Planning at Samsung Electronics. “This new memory solution forms part of our drive toward developing core technologies for high-stack HBM and providing technological leadership for the high-capacity HBM market in the AI era.”

The HBM3E 12H applies advanced thermal compression non-conductive film (TC NCF), allowing the 12-layer products to have the same height specification as 8-layer ones to meet current HBM package requirements. The technology is anticipated to have added benefits especially with higher stacks as the industry seeks to mitigate chip die warping that come with thinner die. Samsung has continued to lower the thickness of its NCF material and achieved the industry’s smallest gap between chips at seven micrometers (µm), while also eliminating voids between layers. These efforts result in enhanced vertical density by over 20% compared to its HBM3 8H product.

Samsung’s advanced TC NCF also improves thermal properties of the HBM by enabling the use of bumps in various sizes between the chips. During the chip bonding process, smaller bumps are used in areas for signaling and larger ones are placed in spots that require heat dissipation. This method also helps with higher product yield.

As AI applications grow exponentially, the HBM3E 12H is expected to be an optimal solution for future systems that require more memory. Its higher performance and capacity will especially allow customers to manage their resources more flexibly and reduce total cost of ownership (TCO) for datacenters. When used in AI applications, it is estimated that, in comparison to adopting HBM3 8H, the average speed for AI training can be increased by 34% while the number of simultaneous users of inference services can be expanded more than 11.5 times.¹

Samsung has begun sampling its HBM3E 12H to customers and mass production is slated for the first half of this year.

¹ Based on internal simulation results

Samsung Electronics, a world leader in advanced memory technology, today held its annual Memory Tech Day, showcasing industry-first innovations and new memory products to accelerate technological advancements across future applications — including the cloud, edge devices and automotive vehicles.

Attended by about 600 customers, partners and industry experts, the event served as a platform for Samsung executives to expand on the company’s vision for “Memory Reimagined,” covering long-term plans to continue its memory technology leadership, outlook on market trends and sustainability goals. The company also presented new product innovations such as the HBM3E Shinebolt, LPDDR5X CAMM2 and Detachable AutoSSD.

Jung-Bae Lee, President and Head of Memory Business at Samsung Electronics, used his keynote address to expand on how Samsung will overcome the challenges of the hyperscale era through innovations in new transistor structures and materials. For example, Samsung is currently preparing new 3D structures for sub-10-nanometer (nm) DRAM, allowing larger single-chip capacities that can exceed 100 gigabits (Gb). Following its 12nm-class DRAM that began mass production in May, 2023, Samsung is working on its next-generation 11nm-class DRAM, which is set to offer the industry’s highest density.

NAND flash breakthroughs that will shrink cell sizes and refine channel hole etching techniques are also in development, with the goal of ushering in 1,000-layer vertical NAND (V-NAND). Development is on track for Samsung’s ninth-generation V-NAND to provide the industry’s highest layer count based on a double-stack structure. The company has secured a functional chip for the new V-NAND and plans to start mass production early next year.

“The new era of hyperscale AI has brought the industry to a crossroads where innovation and opportunity intersect, presenting a time with potential for great leaps forward, despite the challenges,” said Lee. “Through endless imagination and relentless perseverance, we will continue our market leadership by driving innovation and collaborating with customers and partners to deliver solutions that expand possibilities.”

Introducing HBM3E ‘Shinebolt’

Today’s cloud systems are evolving to optimize compute resources, which require high-performance memory to handle high capacity, bandwidth and virtual storage capabilities. Building on Samsung’s expertise in commercializing the industry’s first HBM2 and opening the HBM market for high-performance computing (HPC) in 2016, the company today revealed its next-generation HBM3E DRAM, named Shinebolt.

Samsung’s Shinebolt will power next-generation AI applications, improving total cost of ownership (TCO) and speeding up AI-model training and inference in the data center. The HBM3E boasts an impressive speed of 9.8 gigabits-per-second (Gbps) per pin speed, meaning it can achieve transfer rates exceeding up to more than 1.2 terabytes-per-second (TBps).

In order to enable higher layer stacks and improve thermal characteristics, Samsung has optimized its non-conductive film (NCF) technology to eliminate gaps between chip layers and maximize thermal conductivity.

Samsung’s 8H and 12H HBM3 products are currently in mass production and samples for Shinebolt are shipping to customers. Leaning into its strength as a total semiconductor solutions provider, the company also plans to offer a custom turnkey service that combines next-generation HBM, advanced packaging technologies and foundry offerings together.

Other products highlighted at the event include the 32Gb DDR5 DRAM with the industry’s highest capacity, the industry’s first 32Gbps GDDR7 and the petabyte-scale PBSSD, which offers a significant boost to storage capabilities for server applications.

Redefining Edge Devices Through Powerful Form Factors

In order to process data-intensive tasks, today’s AI technologies are moving toward a hybrid model that allocates and distributes workload among cloud and edge devices. Accordingly, Samsung introduced a range of memory solutions that support high-performance, high-capacity, low-power and small form factors at the edge.

In addition to the industry’s first 7.5Gbps LPDDR5X CAMM2¹ — which is expected to be a true game changer in the next-generation PC and laptop DRAM market — the company also showcased its 9.6Gbps LPDDR5X DRAM, LLW² DRAM specialized for on-device AI, next-generation Universal Flash Storage (UFS), and the high-capacity Quad-Level Cell (QLC) SSD BM9C1 for PCs.

Paving the Road for Automotive Memory Solutions Leadership

With advancements in autonomous driving solutions, market demand is also rising for high-bandwidth, high-capacity DRAM and Shared SSDs, which share data with multiple System on Chips (SoCs).  Samsung presented its Detachable AutoSSD that allows data access from a single SSD to multiple SoCs through virtual storage.

The Detachable AutoSSD supports sequential read speed of up to 6,500 megabytes-per-second (MBps) with 4TB of capacity. As it comes in a detachable form factor, the SSD makes upgrades and adjustments easier for vehicle users and manufacturers. Samsung also displayed automotive memory solutions such as high-bandwidth GDDR7 and LPDDR5X with a more compact package size.

Technology That Makes Technology Sustainable

As part of its commitment to minimizing environmental impact, Samsung underscored a variety of innovations within its semiconductor operations that will contribute to increased energy efficiency for customers and consumers.

The company plans to secure ultra-low-power memory technologies that can decrease power consumption in data centers, PCs and mobile devices, while using recycled materials in portable SSD products to reduce its carbon footprint. Samsung’s next-generation solutions, such as the PBSSD, will also help reduce energy usage for server systems as they maximize space efficiency and rack capacity.

While collaborating with stakeholders across the semiconductor value chain, including customers and partners, Samsung’s semiconductor business will continue to play an active role in tackling global climate issues through its sustainability initiative, “technology that makes technology sustainable.”

To learn more about Samsung Semiconductor’s solutions and Samsung Memory Tech Day 2023, please visit: https://semiconductor.samsung.com/events/techday-memory-2023/. The recap of the event will be posted at a later date.

¹ CAMM: Compression Attached Memory Module.
² LLW: Low Latency Wide I/O.

“H-Cube solution, which is jointly developed with Samsung Electro-Mechanics (SEMCO) and Amkor Technology, is suited to high-performance semiconductors that need to integrate a large number of silicon dies,” said Moonsoo Kang, Senior Vice President and Head of Foundry Market Strategy Team at Samsung Electronics. “By expanding and enriching the foundry ecosystem, we will provide various package solutions to find a breakthrough in the challenges our customers are facing.”

“In today’s environment where system integration is increasingly required and substrate supplies are constrained, Samsung Foundry and Amkor Technology have successfully co-developed H-Cube to overcome these challenges,” said JinYoung Kim, Senior Vice President of Global R&D Center at Amkor Technology. “This development lowers barriers to entry in the HPC/AI market and demonstrates successful collaboration and partnership between the foundry and outsourced semiconductor assembly and test (OSAT) company.”

H-Cube Structure and Features

2.5D packaging enables logic chips or high-bandwidth memory (HBM) to be placed on top of a silicon interposer in a small form factor. Samsung’s H-Cube technology features a hybrid substrate combined with a fine-pitch substrate which is capable of fine bump connection, and a High-Density Interconnection (HDI) substrate, to implement large sizes into 2.5D packaging.

With the recent increase in specifications required in the HPC, AI and networking application market segments, large-area packaging is becoming important as the number and size of chips mounted in one package increases or high-bandwidth communication is required. For attachment and connection of silicon dies including the interposer, fine-pitch substrates are essential but prices rise significantly following an increase in size.

H-Cube Package Structure Concept

When integrating six or more HBMs, the difficulty in manufacturing the large-area substrate increases rapidly, resulting in decreased efficiency. Samsung solved this problem by applying a hybrid substrate structure in which HDI substrates that are easy to implement in large-area are overlapped under a high-end fine-pitch substrate.

By decreasing the pitch of solder ball, which electrically connects the chip and the substrate, by 35% compared to the conventional ball pitch, the size of fine-pitch substrate can be minimized, while adding HDI substrate (module PCB) under the fine-pitch substrate to secure connectivity with the system board.

In addition, to enhance the reliability of the H-Cube solution, Samsung applied its proprietary signal/power integrity analysis technology that can stably supply power while minimizing the signal loss or distortion when stacking multiple logic chips and HBMs.

Looking ahead, in cooperation with its ecosystem partners, Samsung will hold its 3^rd Annual ‘Samsung Advanced Foundry Ecosystem (SAFE) Forum’ virtually on November 17 (PST).

For pre-registration on the SAFE forum, please visit https://www.samsungfoundry.com.