Inyoung Kim – Samsung Global Newsroom

[Editorial] Packaging with a Punch

Samsung Newsroom — Tue, 14 Apr 2015 19:00:55 +0000

Samsung’s Semiconductor Series Part 3

Building state-of-the-art semiconductor chips is one thing but making them into the actual square chips we’re familiar with involves a lot of high-tech, too. This process is called packaging, or back-end manufacturing, where chips are essentially sliced off of the silicon wafer, wired up and encased in epoxy for protection.

Let’s say you have a nice order of milkshake that you want to chug down right now. Organic ingredients with crush-ins of your liking, whatever floats your boat. For that, you would need an efficient apparatus (a.k.a. big enough straw) that can deliver a satisfactory flow of sips, preferably an insulated cup that will keep the frothy integrity of the beverage and temperature-resistant nerves that can hold up to the huge amount of milkshake intake against a massive brain freeze. Similar elements and materials are taken into consideration when chips are packaged. Well, okay, it gets way more complicated with semiconductors, but you get the point.

With the amount of data that need to be processed and the speed that is required today, we want to make sure we offer device manufacturers and consumers the total package, in every sense of the phrase, so that the packaging complements the advanced silicon technology inside. This would also determine the size of the final chip. So yes, packaging solutions, even for semiconductor chips, does matter.

Here are some cool examples of Samsung’s approach to this technology.

Through Silicon Via (TSV) – We talked about increasing cell density on a single chip for higher capacities but another way to achieve that is to stack individual chip dies in a single package. In doing so, the dies are ground from the back as thin as possible, down to several micrometers, so as to minimize the height of the final product.

Instead of the traditional method of connecting the stacked dies externally, we can now pierce hundreds of tiny holes through DRAM dies and then vertically connect them through the holes, allowing faster data processing with less power consumed. This means that if data were in a building, it can just take the elevator downstairs instead of working its way out to the fire escape. Remember, we’re still working in microscopic scales.

TSV allows approximately twice the speed with about half the power compared to packages using the traditional wire bonding. Again, less space, less power consumption and faster data — another reason our DDR4 DRAM using TSV are so awesome.

ePoP – Sleeker mobile devices mean scarcer space for components, so consolidation is very much desired. As such, even chips with different functions can get bundled together and we’ve seen packages come in forms of eMMC (embedded multi-media card: NAND+controller), eMCP (embedded multi-chip package: DRAM+NAND) or PoP (package on package: AP+DRAM). Samsung’s broad chip portfolio encompassing DRAM, NAND and AP, as well as our advanced packaging capabilities in-house, has naturally given us a huge advantage in this department.

Wonder why there aren’t any packages mentioned above incorporating NAND memory and APs? An active AP can get as hot as 80 to 100℃ whereas NAND would normally get ‘fried’ at that temperature. Because of NAND’s low resistance to heat, it’s been considered that it cannot be in the same package as the AP.

Well, guess what — with an out-of-the-box approach and some new techniques, earlier this year, Samsung was able to introduce the industry’s first ePoP (embedded package on package) memory that can be stacked directly on top of an AP.

Our ePoP memory packs a LPDDR3 DRAM and an eMMC together, dramatically shrinking traditional area configurations by about 40 percent. Thanks to its efficiency and small footprint, Samsung’s ePoP memory is now finding itself on board of wearables as well as high-end mobile devices.

Samsung’s Semiconductor Series

Read Part 1. The Itsy-Bitsy Mighty Chip in a Great Big Digital World

Read Part 2. Physics Busting at Its Seams

[Editorial] Physics Busting at Its Seams

Samsung Newsroom — Thu, 09 Apr 2015 19:00:42 +0000

Samsung’s Semiconductor Series Part 2

Read Part 1

Semiconductors have been in a race to drive up both product performance and process manufacturing efficiency. Enter the mobile era, the market clamored for smaller and more powerful devices that would make the most out of their battery life. As the inside of such devices became prime real estate, components had to follow suit.

The convention was to shorten the distance between the circuitry. That means faster data transfers that require less energy, has more compact configurations and yet has the same capacity became possible. Fabrication productivity also got a boost as technology generations progressed.

While market needs catalyzed innovation and aggressive scaling in semiconductors, bringing digital experiences into the palms of our hands, chip fabrication methods quickly ran into a whole bunch of walls—or the lack of them. With details shrinking down to the billionth of a meter, it came to a point where traditional materials wouldn’t work anymore, electric charges started leaking and signals were getting crosstalk. In other words, scaling down the technology any further would gravely compromise the information being stored or waste the energy being consumed.

Our engineers couldn’t really defy the laws of physics. But they were able to bring about new designs and fabrication expertise in semiconductor technology that opened up meaningful opportunities for the industry.

14nm FinFET AP (application processor) – A warm and gooey marshmallow between two graham crackers is good enough as it is but if you make your s’more ‘denser,’ the crackers are brought closer together and the marshmallow gets squished up. That’s kind of what happened with the channel structures of transistors for FinFET. And no, the channel did not ooze out.

In February, we came out with the industry’s first mobile application processor (AP) based on advanced 14nm FinFET technology. By raising a ‘fin’ over the conducting channel and wrapping it over with the gate, the new structure addresses the problems of current leakage, or short-channel effect, that comes with finer technologies, while demonstrating greater power advantages and performance levels over our previous 20nm process technology. With our 14nm FinFET AP out in the hands of consumers, we’re staying busy prepping for 10nm FinFETs and beyond.

20nm DRAM (Dynamic Random Access Memory) – For decades, the semiconductor industry had followed the pattern of doubling the density of ICs (integrated circuit) every two years. But delivering new technology refined enough for mass production got painstakingly harder. Due to limitations especially in the current technology of drawing crazy-thin lines, namely the lithography process, the 25nm design rule is where the industry thought to be the limit for DRAMs. It had been so for nearly two years. We were stuck.

Then, in 2014, came a breakthrough. Bleeding-edge methods such as modified double patterning and atomic layer deposition were introduced, heralding the arrival of the industry’s first 20nm DRAM. Contrary to common belief, we were able to utilize existing lithography tools, keeping costs viable as well. Not only was this a major breakthrough, but it also paves the way for sub-20nm nodes. We are currently the only manufacturer with this technology and are offering a full DRAM lineup for PC and enterprise systems as well as mobile device customers.

3D V-NAND (NAND flash memory) – Let’s say you have a single-story dormitory that you sectioned off for a number of occupants. You needed to accommodate more people, so rooms got smaller and the walls thinner. But tiny dorm rooms with thin walls are no fun at all. So what do you do? You build a skyscraper instead and give each of your tenants the entire floor, of course. All of a sudden, you don’t have to be fighting for space anymore and even better, everybody’s happy and much more productive. Voilà, 3D V-NAND flash memory.

Samsung is the first and still is the only company providing V-NAND products, which feature vertically stacked NAND flash cells. The technology marks a major milestone in memory technology as it overcomes the scaling limitations for conventional 2D planar structures, as well as drastically mitigating development time and resources. Even the first generation V-NAND demonstrated at least twice and up to ten times the reliability while also doubling its write performance. And don’t worry; a few dozen additional cell layers won’t affect the thickness of the final chip at all. Our second generation V-NAND products have also been very well received in the market, especially for applications in today’s SSDs that are equipped for the most demanding tasks.

ISOCELL (CMOS image sensors) – Between pixel size and image quality, there always was a delicate balance to maintain. A good image sensor will capture as much light, or photons, as possible, as accurately as possible through individual pixels within the sensor array. Theoretically, more pixels and larger sensor size would guarantee better picture qualities. However, we’re living in a mobile world. Since smaller pixel sizes come at the expense of the amount of light received, increasing the light sensitivity of each pixel has been the focus of image sensor development so far. Another problem with size; as pixels got packed closer together, photons that had been absorbed would wander into adjacent cells, making pictures blurry or diminishing color fidelity.

Introduced in 2014, our proprietary solution, ISOCELL, was to form a physical barrier between neighboring pixels so that more light is absorbed into the pixels correctly. This results in sharper and richer picture quality. The walls also create a wider chief ray angle (CRA) that reduces the height of the module. In other words, the pixels can afford to be less deep since they can capture those little photons hitting the pixel at a wider angle that would otherwise wander off to the pixel next door. All of these qualities make ISOCELL image sensors ideal for today’s compact devices.

[Editorial] The Itsy-Bitsy Mighty Chip in a Great Big Digital World

Samsung Newsroom — Tue, 07 Apr 2015 19:00:29 +0000

Samsung’s Leadership in the Semiconductor Industry Part 1

“Innovation” may probably be one of the most over-used buzz words of our generation. It seems that we encounter ‘innovation’ daily. In defense of those in the IT world, though, it’s just testament of how fast technologies are evolving. Their life cycles are getting increasingly shorter and breakthroughs are getting that much more difficult to come by. The good news is that engineers are innate problem-solvers, and thanks to them, technology continues to move forward, even in semiconductors down at the nanometer (nm; one billionth of a meter) scale.

In this three-part series, we’ll explore the feats in the semiconductor industry and how Samsung Electronics has tackled some of the most mind-boggling challenges in chip technology.

From our connected world of “things,” more than a whopping 400 ZB of data will be generated by 2018. Given that an average internet user would currently go through about 30 gigabytes (GB) of data a month—sharing emails, HD videos, presentations, copious amount of photos and what have you—this is roughly the equivalent of having the entire population of China frolic in the internet for about nine months. Adding to that, consumers will continue to want smarter connected devices capable of pumping out even more data—50 billion devices by 2020 according to a projection*.

Datacenters that actually have to shoulder most of the job will increasingly have a hard time keeping up with this snowballing trend. About 3.1 zettabytes (ZB) of data traffic went through datacenters globally in 2013**. By 2018, that amount is expected to nearly triple to 8.6 ZB. On top of the sheer amount of data to be processed, the need for electricity and space for these facilities also climb up. If these trends continue, industry calls for some serious innovation from hardware at the system level all the way up to consumer devices.

Taking the charge in rewriting the way we process data is no small undertaking. But it’s something that we, Samsung Electronics, actually can be bold enough to dare. Not only do we offer awesome consumer electronics, but we also have the cutting-edge component solutions up our sleeves—the very chips that hum behind the scenes of our data-driven world. To us, this is our innovation. And we’re pretty serious about it.

The advancements of today’s electronic devices have become more interesting than ever and semiconductors have risen as heroes of this progress. But it’s a little-known fact that Samsung has been a veteran in this field for more than 40 years. In fact, Samsung has been the leading memory manufacturer since 1993 (that’s 23 consecutive years!) and are the second largest semiconductor company in the world. Today, Samsung is the only company that offers a comprehensive portfolio of component solutions spanning from DRAM and NAND flash memory, logic products such as mobile application processors (AP), CMOS image sensors (CIS), display driver ICs (DDI), near field communication (NFC) chips to LED light sources, just to name a few.

Earlier in February this year, Dr. Kinam Kim, Samsung’s Semiconductor Business president and IEEE (Institute of Electrical and Electronics Engineers) fellow, talked about “silicon technologies and solutions for the data-driven world” in his keynote during the ISSCC (International Solid State Circuit Conference) in San Francisco. Dr. Kim addressed the crowd of eager engineers in the audience on the advancements and opportunities in chip technology. Although he spoke mainly about the developments within the industry at large, Samsung’s footprint in the landscape definitely shined through.

Despite their small mundane appearances, the level of sophistication and sheer capabilities that our chips hold keep us excited. And the ways they make a difference in our lives will keep us going.

*Source: Cisco The Internet of Things: How the Next Evolution of the Internet Is Changing Everything, 2011

**Source: Cisco Global Cloud Index: Forecast and Methodology, 2013-2018, 2014