The research was led by Samsung Advanced Institute of Technology (SAIT) in close collaboration with Samsung Electronics Foundry Business and Semiconductor R&D Center. The first author of the paper, Dr. Seungchul Jung, Staff Researcher at SAIT, and the co-corresponding authors Dr. Donhee Ham, Fellow of SAIT and Professor of Harvard University and Dr. Sang Joon Kim, Vice President of Technology at SAIT, spearheaded the research.

In the standard computer architecture, data is stored in memory chips and data computing is executed in separate processor chips.

In contrast, in-memory computing is a new computing paradigm that seeks to perform both data storage and data computing in a memory network. Since this scheme can process a large amount of data stored within the memory network itself without having to move the data, and also because the data processing in the memory network is executed in a highly parallel manner, power consumption is substantially reduced. In-memory computing has thus emerged as one of the promising technologies to realize next-generation low-power AI semiconductor chips.

For this reason, research on in-memory computing has been intensely pursued worldwide. Non-volatile memories, in particular RRAM (Resistive Random Access Memory) and PRAM (Phase-change Random Access Memory), have been actively used for demonstrating in-memory computing. By contrast, it has so far been difficult to use MRAM ─ another type of non-volatile memory ─ for in-memory computing despite MRAM’s merits such as operation speed, endurance and large-scale production. This difficulty stems from the low resistance of MRAM, due to which MRAM cannot enjoy the power reduction advantage when used in the standard in-memory computing architecture.

(From left) Dr. Donhee Ham, Fellow of SAIT and Professor of Harvard University, Dr. Seungchul Jung, Staff Researcher at SAIT and Dr. Sang Joon Kim, Vice President of Technology at SAIT

The Samsung Electronics researchers have provided a solution to this issue by an architectural innovation. Concretely, they succeeded in developing an MRAM array chip that demonstrates in-memory computing, by replacing the standard, ‘current-sum’ in-memory computing architecture with a new, ‘resistance sum’ in-memory computing architecture, which addresses the problem of small resistances of individual MRAM devices.

Samsung’s research team subsequently tested the performance of this MRAM in-memory computing chip by running it to perform AI computing. The chip achieved an accuracy of 98% in classification of hand-written digits and a 93% accuracy in detecting faces from scenes.

By ushering MRAM ─ the memory which has already reached commercial-scale production embedded in the system semiconductor fabrication ─ into the realm of in-memory computing, this work expands the frontier of the next-generation low-power AI chip technologies.

The researchers have also suggested that not only can this new MRAM chip be used for in-memory computing, but it also can serve as a platform to download biological neuronal networks. This is along the line of the neuromorphic electronics vision that Samsung’s researchers recently put forward in a perspective paper published in the September 2021 issue of the journal Nature Electronics.

“In-memory computing draws similarity to the brain in the sense that in the brain, computing also occurs within the network of biological memories, or synapses, the points where neurons touch one another,” said Dr. Seungchul Jung, the first author of the paper. “In fact, while the computing performed by our MRAM network for now has a different purpose from the computing performed by the brain, such solid-state memory network may in the future be used as a platform to mimic the brain by modeling the brain’s synapse connectivity.”

As highlighted in this work, by building on its leading memory technology and merging it with system semiconductor technology, Samsung plans to continue to expand its leadership in next-generation computing and AI semiconductors.

During a keynote speech at the 2018 IEEE* International Electron Devices Meeting (IEDM), Dr. ES Jung, president and head of Foundry Business at Samsung Electronics, shared his vision that the next industrial revolution can only happen by the continuous evolution of semiconductor technology.

In his presentation “Fourth Industrial Revolution and Foundry: Challenges and Opportunities”, Dr. Jung explained that the evolution of advanced foundry technologies will be crucial to enable the design and manufacture of innovative semiconductor products that will take our everyday life into new and previously unthought-of directions.

New and exciting applications such as AI, cloud computing, autonomous vehicles, and smart home require high-level technologies including sophisticated design and system level optimization.

Dr. Jung discussed the increased complexities of semiconductor technology that has altered the role of the semiconductor foundry from a conventional wafer manufacturing business to a total solution provider. Today, foundries are providing value-added services, especially in the areas of design service and infrastructure, product engineering, and packaging/testing.

Semiconductors have evolved to be faster in speed, higher in density, and lower in power consumption, allowing a wide range of new and innovative applications. In addition, to analyze exponentially growing, unprecedented amounts of data, new memory architectures and completely new schemes of computation, such as neuromorphic computing, have to be developed.

“None of these technological advancements would have been possible without collaboration across the entire semiconductor industry” emphasized Dr. Jung. “This collaboration is paramount between material, equipment, electronic devices, government, universities, research centers, and consortiums, to ensure the success in the upcoming 4^th industrial revolution.”

New Technological Milestones

Dr. Jung also introduced some of recent research and development in future silicon technology, including MRAM, a non-volatile memory solution embedded in conventional logic process, and 3nm Gate-All-Around (GAA) technology.

MRAM is one of the examples of new semiconductor devices that consume much less power. As memory density becomes higher, MRAM’s power efficiency becomes more prominent, consuming only 0.5% of power compared to SRAM at 1,024Mb. MRAM also has smaller cell area, which allows design flexibility.

Samsung’s unique GAA technology called Multi-Bridge-Channel FET(MBCFET) uses vertically stacked multiple nanosheet channels. With variable width of nanosheet, this technology provides not only optimal performance and power characteristics, but also high design flexibility. Furthermore, MBCFET is fabricated using 90% or more of FinFET process with only a few revised masks, allowing easy migration.

Also with one of its newly published papers at 2018 IEDM, Samsung Electronics shared the development progress of 3nm, a successful demonstration of fully functioning high-density SRAM circuit. The development of Samsung’s first process node applying MBCFET technology is on schedule.

For more information, please visit https://www.samsungfoundry.com

* IEEE (Institute of Electrical and Electronics Engineers) is one of the world’s largest associations of technical professionals dedicated to advancing technologies, including electronic engineering, telecommunications, and computer engineering. Link