▲ The leaders of Samsung Foundry Business and Semiconductor R&D Center are holding up three fingers as a symbol of 3nm celebrating the company’s first ever production of 3nm process with GAA architecture.

Samsung Electronics, the world leader in semiconductor technology, today announced that it has started initial production of its 3-nanometer (nm) process node applying Gate-All-Around (GAA) transistor architecture.

Multi-Bridge-Channel FET (MBCFET), Samsung’s GAA technology implemented for the first time ever, defies the performance limitations of FinFET, improving power efficiency by reducing the supply voltage level, while also enhancing performance by increasing drive current capability.

Samsung is starting the first application of the nanosheet transistor with semiconductor chips for high performance, low power computing application and plans to expand to mobile processors.

“Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry’s first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world’s first 3nm process with the MBCFET,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. “We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology.”

▲ (From left) Michael Jeong, Corporate Vice President; Ja-Hum Ku, Corporate Executive Vice President; and Sang Bom Kang, Corporate Vice President at Samsung Foundry Business are holding up 3nm wafers at the production line of Samsung Electronics Hwaseong Campus.

Design-Technology Optimization for Maximized PPA

Samsung’s proprietary technology utilizes nanosheets with wider channels, which allow higher performance and greater energy efficiency compared to GAA technologies using nanowires with narrower channels. Utilizing the 3nm GAA technology, Samsung will be able to adjust the channel width of the nanosheet in order to optimize power usage and performance to meet various customer needs.

In addition, the design flexibility of GAA is highly advantageous for Design Technology Co-Optimization (DTCO),¹ which helps boost Power, Performance, Area (PPA) benefits. Compared to 5nm process, the first-generation 3nm process can reduce power consumption by up to 45%, improve performance by 23% and reduce area by 16% compared to 5nm, while the second-generation 3nm process is to reduce power consumption by up to 50%, improve performance by 30% and reduce area by 35%.

Providing 3nm Design Infrastructure & Services With SAFE Partners

As technology nodes get smaller and chip performance needs grow greater, IC designers face challenges of handling tremendous amounts of data to verify complex products with more functions and tighter scaling. To meet such demands, Samsung strives to provide a more stable design environment to help reduce the time required for design, verification and sign-off process, while also boosting product reliability.

Since the third quarter of 2021, Samsung Electronics has been providing proven design infrastructure through extensive preparation with Samsung Advanced Foundry Ecosystem (SAFE) partners including Ansys, Cadence, Siemens and Synopsys, to help customers perfect their product in a reduced period of time.

Quotes from SAFE Partners

• Ansys, [John Lee, Vice President and General Manager of the Electronics, Semiconductor & Optics Business Unit at Ansys]

“Together, Ansys and Samsung continue to deliver enabling technology for the most advanced designs, now at 3nm with GAA technology. The signoff fidelity of our Ansys multiphysics simulation platform is testament to our continued partnership with Samsung Foundry at the leading edge. Ansys remains committed to delivering the best design experience for our mutual advanced customers.”

• Cadence, [Tom Beckley, Senior Vice President and General Manager, Custom IC & PCB Group at Cadence]

“We congratulate Samsung on this 3nm GAA production release milestone. Cadence worked closely with Samsung Foundry to enable customers to achieve optimal power, performance and area for this node using our digital solutions from library characterization to full digital flow implementation and signoff, all driven by our Cadence Cerebrus AI-based technology to maximize productivity. With our custom solutions, we collaborated with Samsung to enable and validate a full AMS flow to enhance productivity from circuit design and simulation through automated layout. We look forward to continuing this collaboration to achieve more tapeout successes.”

• Siemens EDA, [Joe Sawicki, Executive Vice President for the IC-EDA segment of Siemens Digital Industries Software]

“Siemens EDA is pleased to have collaborated with Samsung to help ensure that our existing software platforms also work on Samsung’s new 3-nanometer process node since the initial development phase. Our longtime partnership with Samsung through the SAFE program generates significant value for our mutual customers, by certification of Siemens industry-leading EDA tools at 3nm.”

• Synopsys, [Shankar Krishnamoorthy, General Manager and Corporate Staff for the Silicon Realization Group at Synopsys]

“Through our long-standing, strategic collaboration with Samsung Foundry, we are enabling our solutions to support Samsung’s advanced processes, helping our mutual customers significantly accelerate their design cycles. Our support for Samsung’s 3nm process with GAA architecture continues expanding, now with our Synopsys Digital Design, Analog Design and IP products, enabling customers to deliver differentiated SoCs for key high-performance computing applications.”

¹ For more information on Design Technology Co-Optimization (DTCO), please see below links:

Find the optimal for the best. Part 1

Find the optimal for the best. Part 2

Samsung Electronics, a world leader in advanced semiconductor technology, today unveiled plans for continuous process technology migration to 3- and 2-nanometer (nm) based on the company’s Gate-All-Around (GAA) transistor structure at its 5^th annual Samsung Foundry Forum (SFF) 2021.

With a theme of Adding One More Dimension, the multi-day virtual event is expected to draw over 2,000 global customers and partners. At this year’s event, Samsung will share its vision to bolster its leadership in the rapidly evolving foundry market by taking each respective part of foundry business to the next level: process technology, manufacturing operations and foundry services.

“We will increase our overall production capacity and lead the most advanced technologies while taking silicon scaling a step further and continuing technological innovation by application,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics.” Amid further digitalization prompted by the COVID-19 pandemic, our customers and partners will discover the limitless potential of silicon implementation for delivering the right technology at the right time.”

GAA Is Ready for Customers’ Adoption – 3nm MP in 2022, 2nm in 2025

With its enhanced power, performance and flexible design capability, Samsung’s unique GAA technology, Multi-Bridge-Channel FET (MBCFET^TM), is essential for continuing process migration. Samsung’s first 3nm GAA process node utilizing MBCFET will allow up to 35 percent decrease in area, 30 percent higher performance or 50 percent lower power consumption compared to the 5nm process. In addition to power, performance and area (PPA) improvements, as its process maturity has increased, 3nm’s logic yield is approaching a similar level to the 4nm process, which is currently in mass production.

Samsung is scheduled to start producing its customers’ first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023. Newly added to Samsung’s technology roadmap, the 2nm process node with MBCFET is in the early stages of development with mass production in 2025.

FinFET for CIS, DDI, MCU – 17nm Specialty Process Technology Debuts

Samsung Foundry is continuously improving its FinFET process technology to support specialty products with cost-effective and application-specific competitiveness. A good example of this is the company’s 17nm FinFET process node. In addition to the intrinsic benefits afforded by FinFET, the process node has excellent performance and power efficiency leveraging a 3D transistor architecture. Consequently, Samsung’s 17nm FinFET provides up to 43 percent decrease in area, 39 percent higher performance or a 49 percent increase in power efficiency compared to the 28nm process.

Additionally, Samsung is advancing its 14nm process in order to support 3.3V high voltage or flash-type embedded MRAM (eMRAM) which enables increased write speed and density. It will be a great option for applications such as micro controller units (MCUs), IoT and wearables. Samsung’s 8nm radio frequency (RF) platform is expected to expand the company’s leadership in the 5G semiconductor market from sub-6GHz to mmWave applications.

Looking ahead, in cooperation with its ecosystem partners, Samsung Foundry’s SAFE Forum will be held virtually in November 2021.

A transistor is a semiconductor device used to transform the digital information coded in the binary system into electric signals. A transistor is composed of a ‘channel’ in which the electric current flows between the semiconductor’s source and its drain and a ‘gate’ for managing the electric current traveling through the channel. The gate generates binary system data by amplifying electric signals and also working as a switch. Because of this, the transistor is essentially the basic element of a semiconductor chip.

All digital information, be it in the form documents, photos or videos, is in fact a composed of the binary numeral system, which only uses two symbols, ‘0’ and ‘1’.

In order to increase the number of semiconductor chips mounted on the limited surface of a silicon (Si) substrate, the size of each semiconductor chip naturally needs to be decreased. Furthermore, in order to fit more new and complex functions into each semiconductor chip, the very basic element transistor must become smaller and its power consumption must be minimized to provide the longest possible battery lifespan, as well as reduced heat and electric charges. As electricity consumption is dependent on operating voltage, transistors have been developed so as to decrease operating voltage. Therefore, the history of the semiconductor is synonymous with the history of creating transistors that are smaller, faster and that consume less electricity.

The history of the development of the semiconductor is synonymous with the history of creating transistors that are smaller, faster and that consume less electricity. From the left, Planar Transistor, Fully Depleted (Fin) Transistor, and GAA Transistor

The most widely used transistor in the current semiconductor industry is the Metal-Oxide-Semiconductor (MOS). It consists of a metal electrode, an oxide insulator and a semiconductor channel. The first MOS transistor was of a planar architecture and was structured so that the gate and the channel made contact on one plane. But, as transistors become smaller, the distance between the source and the drain gets smaller, making it difficult for the gates to work as a switch. This is called a ‘short-channel effect’, and along with limiting voltage reduction, it means that planar transistors can only be applied to 20 or above nanometer nodes (or generations)¹.

In order to overcome the short-channel effect, the Fully Depleted transistor emerged as the next generation of transistor. This transistor uses a thin silicon (Si) channel to avoid the short-channel effect by enhancing the ability of the gate to adjust the channel. Its structure format evolved out of that of the conventional transistor (a gate on a plane channel) to become a thin, rugged structure with a standing rectangular channel that interlocks with gates on three sides. As this thin, standing channel somewhat resembles a fish’s dorsal fin, it is also called the ‘fin transistor’. Samsung has been manufacturing fin transistors since 2012 in a range of sizes, starting at just 14 nanometers.

Whereas a planar transistor only allows the channel and the gate to contact in just one plane, a fin transistor has a 3-dimensional structure that allows three sides of a channel (excluding its bottom) to come into contact with the gates. This increased contact with the gates improves semiconductor performance as well as increasing the reduction of operating voltage, solving the problems brought about by the short-channel effect.

Nevertheless, the fin transistor is now facing limitations after several generations of developments and process transitions. Nowadays, the semiconductor industry is increasingly requiring transistors that can reduce operating voltage even further. Despite the fin transistor’s 3-dimensional structure, that only three of the four sides are in contact with gates is now becoming a limitation, as transistors themselves continue to progress and subsequently get smaller.

The evolution of semiconductor transistors

In order to mitigate the limitations of existing transistors solutions, Samsung has developed a new structure, the Gate-All-Around (GAA). As the name suggests, the GAA is a structure that maximizes gates’ channel-controlling function, as all channels, including the fourth bottom one, are covered by gates. The gates provide a 360-degree coverage of the entire channel area to eliminate the short-channel effect, resulting in reducing operating voltage further.

A typical GAA transistor takes the form of a thin and long nanowire². However, a channel needs to be as wide as possible in order to allow a large amount of current to flow through it, and the small diameter of the nanowire makes obtaining this higher current flow difficult. To overcome this, Samsung created and patented their proprietary MBCFET (Multi-Bridge Channel Field Effect Transistor), an optimized version of the GAA transistor. The MBCFET increases the areas that make contact with gates by aligning wire-formed channel structures as a 2-dimensional nanosheets, which enables simpler device integration as well as increasing the electric current. Samsung’s MBCFET is a competitive transistor structure in that it not only includes the means to mitigate the short-channel effect thanks to the GAA structure, but it also increases performance by expanding the channel area.

Compared to existing 7-nanometer fin transistor process technology, the MBCFET decreases power consumption by 50%, improves performance by 30%, and reduces the area that the transistor takes up by 45%.

The development of GAA transistors, tantamount to the Industrial Revolution of semiconductor technology, is such a difficult process that Samsung is the only company currently offering a future delivery plan. Furthermore, the successful creation of the MBCFET is indicative of Samsung’s global industry-leading technological prowess. It has laid the foundation for transforming the semiconductor industry that was set to stall at the 4-nanometer scale, along with providing core technologies necessary for bringing about the fourth industrial revolution.

With this latest market-leading development, Samsung is paving the way for the future of the industry thanks to its collaborative approach and trailblazing technologies.

As a semiconductor engineer working in an industry that is entering an era of transformation brought about by new technology, I am very excited to see what the future holds.

¹Nanometer is a measurement for a semiconductor. 1 nanometer is equal to one billionth of a meter.

²An ultra-tiny line that has one nanometer in section diameter