▲ The leaders of Samsung Foundry Business and Semiconductor R&D Center are holding up three fingers as a symbol of 3nm celebrating the company’s first ever production of 3nm process with GAA architecture.

Samsung Electronics, the world leader in semiconductor technology, today announced that it has started initial production of its 3-nanometer (nm) process node applying Gate-All-Around (GAA) transistor architecture.

Multi-Bridge-Channel FET (MBCFET), Samsung’s GAA technology implemented for the first time ever, defies the performance limitations of FinFET, improving power efficiency by reducing the supply voltage level, while also enhancing performance by increasing drive current capability.

Samsung is starting the first application of the nanosheet transistor with semiconductor chips for high performance, low power computing application and plans to expand to mobile processors.

“Samsung has grown rapidly as we continue to demonstrate leadership in applying next-generation technologies to manufacturing, such as foundry industry’s first High-K Metal Gate, FinFET, as well as EUV. We seek to continue this leadership with the world’s first 3nm process with the MBCFET,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. “We will continue active innovation in competitive technology development and build processes that help expedite achieving maturity of technology.”

▲ (From left) Michael Jeong, Corporate Vice President; Ja-Hum Ku, Corporate Executive Vice President; and Sang Bom Kang, Corporate Vice President at Samsung Foundry Business are holding up 3nm wafers at the production line of Samsung Electronics Hwaseong Campus.

Design-Technology Optimization for Maximized PPA

Samsung’s proprietary technology utilizes nanosheets with wider channels, which allow higher performance and greater energy efficiency compared to GAA technologies using nanowires with narrower channels. Utilizing the 3nm GAA technology, Samsung will be able to adjust the channel width of the nanosheet in order to optimize power usage and performance to meet various customer needs.

In addition, the design flexibility of GAA is highly advantageous for Design Technology Co-Optimization (DTCO),¹ which helps boost Power, Performance, Area (PPA) benefits. Compared to 5nm process, the first-generation 3nm process can reduce power consumption by up to 45%, improve performance by 23% and reduce area by 16% compared to 5nm, while the second-generation 3nm process is to reduce power consumption by up to 50%, improve performance by 30% and reduce area by 35%.

Providing 3nm Design Infrastructure & Services With SAFE Partners

As technology nodes get smaller and chip performance needs grow greater, IC designers face challenges of handling tremendous amounts of data to verify complex products with more functions and tighter scaling. To meet such demands, Samsung strives to provide a more stable design environment to help reduce the time required for design, verification and sign-off process, while also boosting product reliability.

Since the third quarter of 2021, Samsung Electronics has been providing proven design infrastructure through extensive preparation with Samsung Advanced Foundry Ecosystem (SAFE) partners including Ansys, Cadence, Siemens and Synopsys, to help customers perfect their product in a reduced period of time.

Quotes from SAFE Partners

• Ansys, [John Lee, Vice President and General Manager of the Electronics, Semiconductor & Optics Business Unit at Ansys]

“Together, Ansys and Samsung continue to deliver enabling technology for the most advanced designs, now at 3nm with GAA technology. The signoff fidelity of our Ansys multiphysics simulation platform is testament to our continued partnership with Samsung Foundry at the leading edge. Ansys remains committed to delivering the best design experience for our mutual advanced customers.”

• Cadence, [Tom Beckley, Senior Vice President and General Manager, Custom IC & PCB Group at Cadence]

“We congratulate Samsung on this 3nm GAA production release milestone. Cadence worked closely with Samsung Foundry to enable customers to achieve optimal power, performance and area for this node using our digital solutions from library characterization to full digital flow implementation and signoff, all driven by our Cadence Cerebrus AI-based technology to maximize productivity. With our custom solutions, we collaborated with Samsung to enable and validate a full AMS flow to enhance productivity from circuit design and simulation through automated layout. We look forward to continuing this collaboration to achieve more tapeout successes.”

• Siemens EDA, [Joe Sawicki, Executive Vice President for the IC-EDA segment of Siemens Digital Industries Software]

“Siemens EDA is pleased to have collaborated with Samsung to help ensure that our existing software platforms also work on Samsung’s new 3-nanometer process node since the initial development phase. Our longtime partnership with Samsung through the SAFE program generates significant value for our mutual customers, by certification of Siemens industry-leading EDA tools at 3nm.”

• Synopsys, [Shankar Krishnamoorthy, General Manager and Corporate Staff for the Silicon Realization Group at Synopsys]

“Through our long-standing, strategic collaboration with Samsung Foundry, we are enabling our solutions to support Samsung’s advanced processes, helping our mutual customers significantly accelerate their design cycles. Our support for Samsung’s 3nm process with GAA architecture continues expanding, now with our Synopsys Digital Design, Analog Design and IP products, enabling customers to deliver differentiated SoCs for key high-performance computing applications.”

¹ For more information on Design Technology Co-Optimization (DTCO), please see below links:

Find the optimal for the best. Part 1

Find the optimal for the best. Part 2

Samsung attracted more than 200 industry experts from fabless companies and foundry partners, and 16 partner booths displayed advanced foundry technology trends, a significant increase in both numbers compared to last year, representing a more solid customer base of Samsung Foundry as well as greater collaboration in Europe, Middle East, and Africa (EMEA).

Since the EMEA semiconductor market is in demand across a wide range of applications including automotive, consumer, network, and internet-of things (IoT), Samsung introduced various specialty technologies, such as FD-SOI, radio frequency (RF), and embedded memory along with comprehensive portfolio of foundry process nodes.

Samsung Electronics showcased its state-of-the-art foundry platforms that bring together essential technical elements for new-age applications, including 5G, IoT, automotive, and high performance computing (HPC), while expanding its design solution partners to improve global customers’ access to Samsung’s foundry solutions.

“It is a great honor to host our global foundry forum with increasing number of attendees every year. The forum has helped us work closely with our customers and strengthen Samsung’s foundry ecosystem,” said Dr. ES Jung, president and head of foundry business at Samsung Electronics, in the keynote speech. “We will strive to get more customer trust and be the best partner possible to prepare for the future with.”

Given the robustness of the European automotive industry, the foundry platform for automotive semiconductor market is drawing considerable attention, and is expected to rapidly grow to address the increasing demand in the autonomous and electric vehicle market.

Samsung is currently producing several automotive semiconductor products such as driving assistant and infotainment systems, mainly based on its 28-nanometer (nm) FD-SOI and 14nm process nodes. In order to respond to increasing customer inquiries, Samsung plans to expand its automotive process nodes to 8nm in near future.

Samsung is also focusing on functional safety and component reliability, which are critically important in the automotive industry, since any failure could cause serious consequences of accident or injury.

Samsung has already proven its ability to design IPs to meet the required automotive standard, and received the ISO 26262 certification for functional safety in automotive components from TÜV Rheinland. Complying with reliability standard AEC-Q100 and IATF 16969 quality management system, it is also preparing for automotive semiconductor production.

Meanwhile, in cooperation with ecosystem partners, Samsung will host its first SAFE (Samsung Advanced Foundry Ecosystem) Forum on Oct 17 in San Jose, to introduce Samsung’s IP, Electronic Design Automation (EDA), and packaging solutions in detail for foundry partners.

Samsung Electronics, a world leader in advanced semiconductor technology, has announced today its continued commitment to first-pass silicon success for its foundry customers’ chip designs by launching the Samsung Advanced Foundry Ecosystem (SAFE^TM) program.

The SAFE^TM program ensures deep collaboration between the Samsung Foundry, ecosystem partners, and customers to deliver competitive and robust System on Chip (SoC) designs based on certified key design components including Process Design Kit (PDK), reference flows with Design Methodologies(DM), Intellectual Property (IP), and ASIC design support.

“We are very excited to provide the comprehensive, collaborative, and qualified Samsung Advanced Foundry Ecosystem to our customers to enable faster and more reliable SoC design success”, said Jong Shik Yoon, executive vice president of Foundry Technology Development at Samsung Electronics. “Together with our SAFE^TM partners, Samsung Foundry will provide certified design enablement solutions to existing strategic customers as well as innovative, new start-up customers. We welcome all current and future Ecosystem partners to join the new SAFE^TM program.”

The SAFE^TM program is based on three pillars :

• EDA/DM : Provides extensively tested PDKs and reference flows (with design methodologies) that are backed by Samsung Foundry’s certification.
• IP : Provides a full set of silicon qualified, application specific IP offerings from the early stage of process technology development. Customers can view a full list of IP solutions offered through SAFE^TM by accessing Samsung Foundry’s B2B site, CONNECT(https://www.samsungfoundry.com).
• Design Services : Connects mid- to small-sized companies with qualified ASIC design services and support. Using design service partners of SAFE^TM, customers will benefit from easy access to process technology information, competitive price conditions, and committed resources for their SoC design success.

For more information about Samsung Foundry, please visit https://www.samsungfoundry.com

Quotes from SAFE^TM  Partner Companies

• Arm, Gus Yeung, vice president and general manager of Physical Design Group

“The Samsung Advanced Foundry Ecosystem creates significant opportunities for the industry. Through our ongoing collaboration with the Samsung Foundry, we are enabling the ecosystem with access to leadership co-optimized physical IP solutions for enhancing next-generation SoC designs.”

• AlphaHoldings, Donggi Kim, CEO

“It’s honor to be one of the initial member of SAFE. As a Korean design service partner, we are ready to support Samsung Foundry’s ASIC customers more effective way based on long-term collaboration with Samsung Foundry and competencies – leading edge process experiences, customer specific IP, high quality manpower, error free design capabilities, etc.”

• Cadence, KT Moore, vice president, product management

“We’ve collaborated with Samsung Foundry for many years to enable our joint customers to achieve their aggressive design goals. We believe that the new SAFE foundry design program will facilitate innovation and help customers deliver designs to market even faster. Our support for Samsung Foundry’s process technologies continues to expand with our broadened IP portfolio and full EDA tool enablement with comprehensive reference flows.”

• eSilicon, Hugh Durdan, vice president, strategy and products

“Through our Tier 1 ASIC work with Samsung Foundry, we understand Samsung Foundry’s advanced process technologies well. This allows us to offer differentiating IP targeted at the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets using these advanced process technologies.”

• Faraday, Steve Wang, President

“Samsung Foundry provides the most competitive grand ecosystem for the leading edge technologies. Since our establishment in 1993, Faraday has successfully delivered more than 2,200 ASIC mass production projects. Thus we are confident in our ability to leverage the SAFE program, targeting next-generation applications now and beyond.”

• Mentor, Joe Sawicki, vice president, Design to Silicon

“Mentor is proud that it has been the signoff solution for Samsung’s own design efforts over the last two decades and Samsung Foundry since the foundry was launched in 2005. We are pleased to be continuing our close partnership with Samsung as it expands its ecosystem interactions via the Samsung SAFE initiative.”

• Rambus, Luc Seraphin, senior vice president and general manager, Memory and Interfaces Division

“As ASIC and SoC designs continue to increase in complexity, high-speed interfaces are integral to successful design. This strong partnership between Rambus and Samsung across multiple nodes, ensures that we are providing a broad portfolio of high-quality solutions to our end customers. We are pleased to collaborate with Samsung Foundry to provide designers with leading high-speed SerDes and memory PHY IP solutions for easy integration into their chip designs.”

• Synopsys, Deirdre Hanford, co-general manager, Design Group

“Our collaboration with Samsung Foundry since 2005 has enabled mutual customers to deliver state-of-the-art designs across a wide range of Samsung’s process technologies. The SAFE program will help accelerate adoption of Synopsys’ high-quality IP, market-leading tools, and comprehensive design services supporting Samsung Foundry for development of their differentiated SoCs.”

• VeriSilicon, Wayne Dai, President and CEO

“Our experience in shipping high volume SoCs using Samsung 14nm and 10nm FinFET, as well as 28nm FD-SOI process demonstrates that Samsung Foundry has excellent potential for the China market. Now as a charter member of SAFE, we will expand our partnership to a new level enabling us to better support our mutual customers.”