Samsung Electronics, a world leader in advanced semiconductor technology, held its 3^rd Annual Samsung Advanced Foundry Ecosystem (SAFE^TM) Forum 2021 virtually today.

With the theme of ‘Performance Platform 2.0: Innovation, Intelligence, Integration’, Samsung and its foundry ecosystem partners prepared 7 plenary talks and 76 technology sessions focused on three main topics: Gate-All-Around (GAA, Innovation), Artificial Intelligence (AI, Intelligence) and 2.5D/3D (Integration) technologies and the diverse design infrastructures required for high-performance applications.

“In the rapidly changing data-centric era, Samsung and its foundry partners have made great strides responding to increasing customers demand and to support their success by providing powerful solutions,” said Ryan Lee, Senior Vice President and Head of Foundry Design Platform Development at Samsung Electronics. “With the support of our SAFE program, Samsung will lead the realization of the vision ‘Performance Platform 2.0’.”

Starting with a keynote live streaming on November 17, attendees are able to explore a variety of tech sessions and engage with ecosystem partners through the virtual SAFE Forum platform for a month. To register for SAFE forum, please visit https://www.samsungfoundry.com.

SAFE 2021: Performance Platform 2.0

Samsung has concentrated on expanding its foundry ecosystem by focusing on IP, Electronic Design Automation (EDA), Cloud, Design Solution Partner (DSP) and Package solutions necessary for today’s data-driven era. Samsung introduced today its latest SAFE^TM program including:

• SAFE^TM-IP & EDA: Samsung and its foundry ecosystem have reserved over 3,600 IPs and 80 certified EDA tools respectively. These are developed and verified based on the high-standard certification program run by Samsung and participated in by our partners. In order to respond to the demands of high performance applications, Samsung’s foundry ecosystem has developed not only HPC-specific foundation IPs including standard cell libraries and memory compilers but also key IPs, such as over 100Gbps Serializer-Deserializer (SerDes) interface and 2.5D/3D multi-die integration solutions.
  
  With our EDA partners, Samsung has secured design tools optimized for its unique 3-nanometer (nm) GAA process technology and design methodology for integrating multiple dies in 2.5D/3D. Customers can also utilize AI- and machine learning-based EDA technology to systematically manage and analyze design data. To overcome the increasing difficulties of chip design and analysis, Samsung has strengthened cooperation with partners to develop EDA tools and related technologies, such as incorporating GPUs that can efficiently use computing resources required for chip verification.

• SAFE^TM-OSAT: Samsung plans to lead ‘beyond-Moore’ technologies by strengthening various package line-ups such as 2.5D/3D through the expansion of its SAFE-Outsourced Semiconductor Assembly and Test (OSAT) ecosystem. The recent announcement of the co-development of Hybrid-Substrate Cube (H-Cube) solution, which offers efficient integration of 6 HBMs and cost benefit, is one of the successful examples of Samsung foundry’s collaboration with the OSAT community.

• SAFE^TM-Cloud Design Platform: SAFE^TM-CDP, the cloud-based one-stop design platform introduced last year, now supports a hybrid cloud function that can be linked to customers’ conventional design environments.

• SAFE^TM-DSP: Through the SAFE^TM-DSP ecosystem, Samsung and its global partners can actively support global fabless companies to implement their design ideas into custom product by utilizing cutting-edge process technologies as well as high-performance, low-power chip design knowledge.

[Quote from SAFE^TM Partner companies]

• Ansys, Ajei Gopal, CEO

“Today’s chips demand a full multiphysics approach, which requires engineering simulation. Ansys is proud to partner with Samsung to deliver a comprehensive multi-physics analysis flow for Samsung’s multi-die integration initiative. The benefits to joint customers, to the industry – and to the entire world – are tremendous. Semiconductors will drive innovations as varied as autonomous and electric vehicles, artificial intelligence, and mobile technologies, including 5G and beyond.”

• Arm, Simon Segars, CEO

“Our longstanding partnership with Samsung Foundry has been essential for growing business opportunities in many markets for our combined partner ecosystem. This close collaboration continues as we work together to optimize our Armv9 next-generation processors on Samsung Foundry’s leading-edge processes, including GAA, to deliver a best-in-class solution that is optimized for the world of today, and the technologies of tomorrow. Together, we are unlocking new opportunities across HPC, Automotive, AI, and IoT, while also managing rising complexities, enabling faster time to market.”

• Cadence, Lip-Bu Tan, CEO

“The Cadence Intelligent System Design strategy is very well-aligned with Samsung Foundry’s Performance Platform 2.0 with common themes of innovation, pervasive intelligence and integrated solutions. Together, we’re enabling customers to develop and deliver innovative, breakthrough products using Samsung’s most advanced process and packaging technologies, and we look forward to continuing our work with Samsung Foundry to accelerate design successes”

• Siemens EDA, A. J. Incorvaia, Senior Vice President

“The Samsung SAFE event provides an exceptionally valuable venue for the Samsung Foundry ecosystem to meet, share information and identify opportunities to fully leverage Samsung’s cutting-edge process technologies. Siemens EDA looks forward to this year’s Samsung SAFE event and the many opportunities it presents for collaborating with customers and partners to eliminate design obstacles and enhance silicon success.”

• Synopsys, Sassine Ghazi, president and COO

“We see exciting times ahead as software and chip technology come together to create world-changing new products,” said Sassine Ghazi, president and COO of Synopsys. “We have strong programs with Samsung Foundry on 3nm gate-all-around enablement, broad IP certification, AI-assisted chip design and 2.5/3D multi-die design to name just a few. We welcome the strong collaboration opportunities offered by the Samsung SAFE initiative.”

Samsung Electronics, a world leader in advanced semiconductor technology, today unveiled plans for continuous process technology migration to 3- and 2-nanometer (nm) based on the company’s Gate-All-Around (GAA) transistor structure at its 5^th annual Samsung Foundry Forum (SFF) 2021.

With a theme of Adding One More Dimension, the multi-day virtual event is expected to draw over 2,000 global customers and partners. At this year’s event, Samsung will share its vision to bolster its leadership in the rapidly evolving foundry market by taking each respective part of foundry business to the next level: process technology, manufacturing operations and foundry services.

“We will increase our overall production capacity and lead the most advanced technologies while taking silicon scaling a step further and continuing technological innovation by application,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics.” Amid further digitalization prompted by the COVID-19 pandemic, our customers and partners will discover the limitless potential of silicon implementation for delivering the right technology at the right time.”

GAA Is Ready for Customers’ Adoption – 3nm MP in 2022, 2nm in 2025

With its enhanced power, performance and flexible design capability, Samsung’s unique GAA technology, Multi-Bridge-Channel FET (MBCFET^TM), is essential for continuing process migration. Samsung’s first 3nm GAA process node utilizing MBCFET will allow up to 35 percent decrease in area, 30 percent higher performance or 50 percent lower power consumption compared to the 5nm process. In addition to power, performance and area (PPA) improvements, as its process maturity has increased, 3nm’s logic yield is approaching a similar level to the 4nm process, which is currently in mass production.

Samsung is scheduled to start producing its customers’ first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023. Newly added to Samsung’s technology roadmap, the 2nm process node with MBCFET is in the early stages of development with mass production in 2025.

FinFET for CIS, DDI, MCU – 17nm Specialty Process Technology Debuts

Samsung Foundry is continuously improving its FinFET process technology to support specialty products with cost-effective and application-specific competitiveness. A good example of this is the company’s 17nm FinFET process node. In addition to the intrinsic benefits afforded by FinFET, the process node has excellent performance and power efficiency leveraging a 3D transistor architecture. Consequently, Samsung’s 17nm FinFET provides up to 43 percent decrease in area, 39 percent higher performance or a 49 percent increase in power efficiency compared to the 28nm process.

Additionally, Samsung is advancing its 14nm process in order to support 3.3V high voltage or flash-type embedded MRAM (eMRAM) which enables increased write speed and density. It will be a great option for applications such as micro controller units (MCUs), IoT and wearables. Samsung’s 8nm radio frequency (RF) platform is expected to expand the company’s leadership in the 5G semiconductor market from sub-6GHz to mmWave applications.

Looking ahead, in cooperation with its ecosystem partners, Samsung Foundry’s SAFE Forum will be held virtually in November 2021.