As a state-of-the-art facility, NRD-K broke ground in 2022 and is set to become a key research base for Samsung’s memory, system LSI and foundry semiconductor R&D. With its advanced infrastructure, research and product-level verification will be able to take place under one roof. Samsung plans to invest about KRW 20 trillion by 2030 for the complex in an area covering about 109,000 square meters (m²) within its Giheung campus. The complex will also include an R&D-dedicated line scheduled to begin operation in mid-2025.

▲ Young Hyun Jun, Vice Chairman and Head of the Device Solutions Division at Samsung Electronics, gives a speech at the tool-in ceremony for Samsung’s new semiconductor research and development complex (NRD-K) in Giheung, Korea.

“NRD-K will bolster our development speed, enabling the company to create a virtuous cycle to accelerate fundamental research on next-generation technology and mass production. We will lay the foundation for a new leap forward in Giheung, where Samsung Electronics’ 50-year history of semiconductors began, and create a new future for the next 100 years,” said Young Hyun Jun, Vice Chairman and Head of the Device Solutions Division at Samsung Electronics.

“At a time when the importance of win-win partnerships is greater than ever, Applied Materials is committed to accelerating innovation velocity through deep collaboration with Samsung Electronics, working together to drive a new wave of growth for the semiconductor industry,” said Park Gwang-Sun, Head of Applied Materials Korea.

▲ Samsung Electronics Vice Chairman Young Hyun Jun, center, poses for a photo with executives during a tool-in ceremony at the Giheung Campus. * (left) Wanwoo Choi Head of People Team, Taeyang Yoon Chief Safety Officer, Jiwoon Im NRD-K P/J group head, Siyoung Choi Head of Foundry Business, BongHyun Kim DRAM Process Development Team, Jung-Bae Lee head of Memory Business, r, Young Hyun Jun, Vice Chairman and Head of the Device Solutions Division, Yong In Park Head of System LSI Business, Yujin Lee Flash Process Development Team, Seok Woo Nam Corporate President in charge / FAB Engineering & Operations, Jaihyuk Song Device Solutions CTO, HongGyeong Kim Head of Corporate Office.

Samsung’s Giheung campus, located south of Seoul, is the birthplace of the world’s first 64-megabit (Mb) DRAM in 1992, marking the beginning of the company’s semiconductor leadership. The establishment of the new R&D facility will usher in the latest developments in process technology and manufacturing tools, extending the site’s legacy at the forefront of innovation.

▲ Samsung Electronics executives poses for a photo during a tool-in ceremony at the Giheung Campus.

NRD-K will be set up with High NA extreme ultra-violet (EUV) lithography and new material deposition equipment aimed at accelerating the development of next-generation memory semiconductors such as 3D DRAM and V-NAND with more than 1,000 layers. In addition, wafer bonding infrastructure with innovative wafer-to-wafer bonding capabilities is also planned to dock.

Samsung invested a record KRW 8.87 trillion in R&D in the third quarter of this year, and continues to push boundaries to secure competitiveness in future technologies, such as advanced packaging for high bandwidth memory (HBM) production.

Samsung Electronics, a world leader in advanced memory technology, today held its annual Memory Tech Day, showcasing industry-first innovations and new memory products to accelerate technological advancements across future applications — including the cloud, edge devices and automotive vehicles.

Attended by about 600 customers, partners and industry experts, the event served as a platform for Samsung executives to expand on the company’s vision for “Memory Reimagined,” covering long-term plans to continue its memory technology leadership, outlook on market trends and sustainability goals. The company also presented new product innovations such as the HBM3E Shinebolt, LPDDR5X CAMM2 and Detachable AutoSSD.

Jung-Bae Lee, President and Head of Memory Business at Samsung Electronics, used his keynote address to expand on how Samsung will overcome the challenges of the hyperscale era through innovations in new transistor structures and materials. For example, Samsung is currently preparing new 3D structures for sub-10-nanometer (nm) DRAM, allowing larger single-chip capacities that can exceed 100 gigabits (Gb). Following its 12nm-class DRAM that began mass production in May, 2023, Samsung is working on its next-generation 11nm-class DRAM, which is set to offer the industry’s highest density.

NAND flash breakthroughs that will shrink cell sizes and refine channel hole etching techniques are also in development, with the goal of ushering in 1,000-layer vertical NAND (V-NAND). Development is on track for Samsung’s ninth-generation V-NAND to provide the industry’s highest layer count based on a double-stack structure. The company has secured a functional chip for the new V-NAND and plans to start mass production early next year.

“The new era of hyperscale AI has brought the industry to a crossroads where innovation and opportunity intersect, presenting a time with potential for great leaps forward, despite the challenges,” said Lee. “Through endless imagination and relentless perseverance, we will continue our market leadership by driving innovation and collaborating with customers and partners to deliver solutions that expand possibilities.”

Introducing HBM3E ‘Shinebolt’

Today’s cloud systems are evolving to optimize compute resources, which require high-performance memory to handle high capacity, bandwidth and virtual storage capabilities. Building on Samsung’s expertise in commercializing the industry’s first HBM2 and opening the HBM market for high-performance computing (HPC) in 2016, the company today revealed its next-generation HBM3E DRAM, named Shinebolt.

Samsung’s Shinebolt will power next-generation AI applications, improving total cost of ownership (TCO) and speeding up AI-model training and inference in the data center. The HBM3E boasts an impressive speed of 9.8 gigabits-per-second (Gbps) per pin speed, meaning it can achieve transfer rates exceeding up to more than 1.2 terabytes-per-second (TBps).

In order to enable higher layer stacks and improve thermal characteristics, Samsung has optimized its non-conductive film (NCF) technology to eliminate gaps between chip layers and maximize thermal conductivity.

Samsung’s 8H and 12H HBM3 products are currently in mass production and samples for Shinebolt are shipping to customers. Leaning into its strength as a total semiconductor solutions provider, the company also plans to offer a custom turnkey service that combines next-generation HBM, advanced packaging technologies and foundry offerings together.

Other products highlighted at the event include the 32Gb DDR5 DRAM with the industry’s highest capacity, the industry’s first 32Gbps GDDR7 and the petabyte-scale PBSSD, which offers a significant boost to storage capabilities for server applications.

Redefining Edge Devices Through Powerful Form Factors

In order to process data-intensive tasks, today’s AI technologies are moving toward a hybrid model that allocates and distributes workload among cloud and edge devices. Accordingly, Samsung introduced a range of memory solutions that support high-performance, high-capacity, low-power and small form factors at the edge.

In addition to the industry’s first 7.5Gbps LPDDR5X CAMM2¹ — which is expected to be a true game changer in the next-generation PC and laptop DRAM market — the company also showcased its 9.6Gbps LPDDR5X DRAM, LLW² DRAM specialized for on-device AI, next-generation Universal Flash Storage (UFS), and the high-capacity Quad-Level Cell (QLC) SSD BM9C1 for PCs.

Paving the Road for Automotive Memory Solutions Leadership

With advancements in autonomous driving solutions, market demand is also rising for high-bandwidth, high-capacity DRAM and Shared SSDs, which share data with multiple System on Chips (SoCs).  Samsung presented its Detachable AutoSSD that allows data access from a single SSD to multiple SoCs through virtual storage.

The Detachable AutoSSD supports sequential read speed of up to 6,500 megabytes-per-second (MBps) with 4TB of capacity. As it comes in a detachable form factor, the SSD makes upgrades and adjustments easier for vehicle users and manufacturers. Samsung also displayed automotive memory solutions such as high-bandwidth GDDR7 and LPDDR5X with a more compact package size.

Technology That Makes Technology Sustainable

As part of its commitment to minimizing environmental impact, Samsung underscored a variety of innovations within its semiconductor operations that will contribute to increased energy efficiency for customers and consumers.

The company plans to secure ultra-low-power memory technologies that can decrease power consumption in data centers, PCs and mobile devices, while using recycled materials in portable SSD products to reduce its carbon footprint. Samsung’s next-generation solutions, such as the PBSSD, will also help reduce energy usage for server systems as they maximize space efficiency and rack capacity.

While collaborating with stakeholders across the semiconductor value chain, including customers and partners, Samsung’s semiconductor business will continue to play an active role in tackling global climate issues through its sustainability initiative, “technology that makes technology sustainable.”

To learn more about Samsung Semiconductor’s solutions and Samsung Memory Tech Day 2023, please visit: https://semiconductor.samsung.com/events/techday-memory-2023/. The recap of the event will be posted at a later date.

¹ CAMM: Compression Attached Memory Module.
² LLW: Low Latency Wide I/O.

LCA is a methodology for assessing environmental impacts throughout the lifecycle of commercial products, processes, or services, by quantifying the amount of energy, materials and waste discharge. In detail, on its semiconductors’ carbon footprint, Samsung’s LCA covers raw material extraction to chip manufacturing, assembling and testing. Its results are in accordance with ISO 14040, ISO 14044 and ISO 14067 to ensure credibility and transparency.

The carbon footprint is commonly used by Samsung and its customers to recognize the environmental impact across all phases of Samsung’s semiconductor products and can be used as a metric to track and reduce carbon emissions.

“Since 2019, we have been actively mobilizing efforts to measure and reduce the carbon emissions of our key memory and logic solutions,” said Dooguen Song, Executive Vice President of the Environment, Health and Safety (EHS) Center at Samsung Electronics. “By leveraging LCA, we will be able to support our customers to achieve their carbon neutrality, as well as becoming more transparent on the environmental impact of the semiconductors we produce worldwide.”

“As a global expert in energy and environmental certification, DNV is pleased to have partnered with and to congratulate Samsung on successfully establishing its reliable LCA,” said JangSup Lee, CEO of DNV Business Assurance Korea. “Together with global business leaders like Samsung, we will continue to take part in creating a more sustainable environment in the future.”

Since 2019, 37 of Samsung’s semiconductor products received carbon footprint accreditation from the Carbon Trust and UL, 6 of its memory products certified for carbon reduction from Carbon Trust. Samsung’s eco-conscious product portfolio includes DRAM, SSD, embedded storage, mobile SoC, mobile Image Sensor, automotive LED packages.

Leveraging its LCA established at the end of last year, Samsung will quantify the carbon footprints of chips manufactured across all of its global manufacturing, testing and assembly locations in Korea, China and the U.S.

With sustainability at its core, Samsung will expand its LCA to include water and resource footprints to provide a more comprehensive assessment that will ultimately reduce the environmental impact of various applications such as mobile and wearables, data centers, consumer electronics, automotive, communications and more.

“We will continue to enhance our business resilience and maintain a robust business continuity management system to handle not only conventional crises but also newly emerging issues such as global supply chain disturbance,” said Taeyang Yoon, Executive Vice President and Chief Safety Officer (CSO) of DS Division at Samsung Electronics. “Through these efforts, our customers can rely on our leading semiconductor technology even in the most unexpected circumstances.”

A BCMS helps organizations secure business continuity by systematically laying out the steps to resume their business after an unexpected crisis or disaster. The system not only deals with the initial emergency response but also focuses on recovering and resuming its core business activities in the shortest possible timeframe. The ISO 22301 is the international standard for BCMS, representing the highest level of commitment to business continuity and disaster preparedness.

Samsung Electronics worked to advance its BCMS for Hwaseong Campus to meet global standards, in order to better deal with the rapidly changing global environment as well as enhancing the level of trust between Samsung and its customers. As part of this process, Samsung evaluated the risks that could affect its chip business and prepared for them through precautionary exercises such as an emergency drill.

Having received global recognition of its business resilience with the ISO 22301 certification, customer confidence in Samsung is expected to grow. Samsung is planning to attain ISO 22301 certifications for its other semiconductor campuses in Korea and abroad from this year.

“Samsung showed strong will in having a robust business continuity management system, and displayed world-class crisis monitoring and response capabilities,” said SeongHwan Lim, Chief Operating Officer of BSI Korea.

“Our new PM9C1a SSD will deliver a robust combination of superior performance, greater power efficiency and increased security, which are the qualities that matter most to PC users,” said Yong Ho Song, Executive Vice President of Memory Solution Product & Development at Samsung Electronics. “We are committed to creating storage that satisfies the diverse and changing market requirements as we continue to advance innovation in the PC SSD space.”

With top-tier speeds, the PM9C1a SSD is ideal for everyday use as well as for more demanding computing and gaming applications. Leveraging the PCIe 4.0 interface, Samsung’s PM9C1a boasts a 1.6x faster sequential read speed and a 1.8x faster sequential write speed than its previous storage offering (PM9B1), reaching 6,000 megabytes per second (MB/s) and 5,600MB/s, respectively. Additionally, random read and write speeds can support up to 900K input/output operations per second (IOPS) and 1,000K IOPS, respectively.

The PM9C1a also offers up to 70% more power efficiency per watt than its predecessor. This means the new SSD can handle the same amount of tasks using significantly less power. Furthermore, when a notebook PC goes into standby mode, the SSD will use approximately 10% less power.

To address the rising need for stronger security measures, the PM9C1a features powerful security. The SSD supports the Device Identifier Composition Engine (DICE) security standard created by the Trusted Computing Group (TCG), a global organization that develops open standards for computing security. DICE securely generates cryptographic keys inside the SSD, providing device authentication to protect against supply chain attacks — cyberattacks that target companies through vulnerabilities in their supplier network — as well as attestation to prevent any firmware tampering.

Samsung’s PM9C1a SSDs will be available in 256GB, 512GB and 1TB storage capacities in a M.2 form factor (22mm x 30mm, 22mm x 42mm, 22mm x 80mm).

Samsung Electronics today announced the development of its 16-gigabit (Gb) DDR5 DRAM built using the industry’s first 12-nanometer (nm)-class process technology, as well as the completion of product evaluation for compatibility with AMD.

“Our 12nm-range DRAM will be a key enabler in driving market-wide adoption of DDR5 DRAM,” said Jooyoung Lee, Executive Vice President of DRAM Product & Technology at Samsung Electronics. “With exceptional performance and power efficiency, we expect our new DRAM to serve as the foundation for more sustainable operations in areas such as next-generation computing, data centers and AI-driven systems.”

“Innovation often requires close collaboration with industry partners to push the bounds of technology,” said Joe Macri, Senior VP, Corporate Fellow and Client, Compute and Graphics CTO at AMD. “We are thrilled to once again collaborate with Samsung, particularly on introducing DDR5 memory products that are optimized and validated on ‘Zen’ platforms.”

This technological leap was made possible through the use of a new high-κ material that increases cell capacitance and proprietary design technology that improves critical circuit characteristics. Combined with advanced, multi-layer extreme ultraviolet (EUV) lithography, the new DRAM features the industry’s highest die density, which enables a 20 percent gain in wafer productivity.

Leveraging the latest DDR5 standard, Samsung’s 12nm-class DRAM will help unlock speeds of up to 7.2 gigabits per second (Gbps). This translates into processing two 30 gigabyte (GB) UHD movies in just one second.

The new DRAM’s exceptional speed is matched by greater power efficiency. Consuming up to 23 percent less power than the previous DRAM, the 12nm-class DRAM will be an ideal solution for global IT companies pursuing more environment-friendly operations.

With mass production set to begin in 2023, Samsung plans to broaden its DRAM lineup built on this cutting-edge 12nm-class process technology into a wide range of market segments as it continues to work with industry partners to support the rapid expansion of next-generation computing.

“As market demand for denser, greater-capacity storage pushes for higher V-NAND layer counts, Samsung has adopted its advanced 3D scaling technology to reduce surface area and height, while avoiding the cell-to-cell interference that normally occurs with scaling down,” said SungHoi Hur, Executive Vice President of Flash Product & Technology at Samsung Electronics. “Our eighth-generation V-NAND will help meet rapidly growing market demand and better position us to deliver more differentiated products and solutions, which will be at the very foundation of future storage innovations.”

Samsung was able to attain the industry’s highest bit density by significantly enhancing the bit productivity per wafer. Based on the Toggle DDR 5.0 interface* — the latest NAND flash standard — Samsung’s eighth-generation V-NAND features an input and output (I/O) speed of up to 2.4 gigabits per second (Gbps), a 1.2X boost over the previous generation. This will enable the new V-NAND to accommodate the performance requirements of PCIe 4.0, and later, PCIe 5.0.

The eighth-generation V-NAND is expected to serve as the cornerstone for storage configurations that help expand the storage capacity in next-generation enterprise servers, while extending its use into the automotive market where reliability is especially critical.

* Editor’s note: Toggle DDR interface generations — 1.0 (133Mbps), 2.0 (400Mbps), 3.0 (800Mbps), 4.0 (1,200Mbps), 5.0 (2,400Mbps)

The achievement was based on Samsung’s restored financial performance, which is now near pre-pandemic levels, and higher demand for memory due to an increase in data usage. In 2021, Samsung scored a brand value growth of 20% compared to 2020 and this year, continues the double-digit growth. Samsung first entered the top 10 list in 2012, placing in ninth position, and has managed to rise in the chart each year, reaching sixth place in 2017 and fifth place in 2020.

“Samsung Electronics was able to record two consecutive years of double-digit growth in brand value, all thanks to the support from our global customers,” said YH Lee, Executive Vice President and Chief Marketing Officer of Samsung Electronics. “In return, the entire company will work together as a team to provide a better and more satisfying customer experience.”

Various Factors Evaluated by Interbrand To Build the Samsung Brand Value

At the end of 2021, Samsung Electronics merged its SET Division and created the Device eXperience Division to increase synergy among its products and provide a next level of experience to customers. Furthermore, Samsung also launched the Customer eXperience-Multi Device Experience Center to strengthen its multi-device connection experience.

Along with these measures, Samsung has integrated the SmartThings across its product categories, creating an inclusive ecosystem and a multi-device experience. SmartThings also empowers consumers to get the most out of their Samsung devices, as well as third-party products they may already own.

In addition, Samsung’s Future Generation Lab has been created to foster authentic conversations around the activities of the next generation. The insights from the lab have been applied to the products and marketing activities.

As well as innovative products based on consumer experiences, the development of advanced technologies such as artificial intelligence (AI), 5G, automotive and robotics through consistent investment also played a role in Samsung’s growth.

Samsung’s Recognized Efforts in Each Product Division for a Better Customer Experience

Mobile

• Camera innovation of Galaxy S22 series based on customers’ insights, and Nightography campaign rollout Cementing leadership in the foldable mobile phone category
• Partnership with Google and Microsoft to strengthen users’ connected experience
• Respecting the value of user security and privacy through Samsung Knox

Network

• Pioneering network innovation path in virtualization and openness with large-scale commercial experiences
• Driving 5G industry with its market-leading 5G portfolio from RAN and Core to automation tools
• Realizing the ESG commitment through intelligent network solutions for energy efficiency

Visual Display

• Continuing innovation of premium TVs, including Micro LED, the Neo QLED 8K/4K
• Strengthening its product portfolio based on customers’ lifestyle, such as The Frame, The Freestyle
• Providing new gaming experiences to consumers, including the Samsung Gaming Hub and the Odyssey Ark

Home Appliances

• Expanding Bespoke product categories beyond kitchen to entire home including clothing care, floor care and air care
• Delivering sustainability values through its products (achieving high level of energy saving rate for major products, guaranteed warranties for digital inverter compressor, reduced microplastic emission from washing machines in collaboration with Patagonia)
• Creating excitement among Bespoke fans through participation-focused online and offline campaigns

Semiconductor

• Investing in next-generation technologies and production capabilities to ensure stable supplies for cutting-edge applications (constructing new $17B manufacturing line in Texas, KRW 20-trillion R&D complex in Giheung)
• Delivering industry-leading semiconductor innovations that enhance product performance and energy efficiency (industry’s first 3nm GAA mass production)
• Developing innovative memory solutions to address the explosive growth of data-intensive tasks in areas such as AI and ML (CXL memory, HBM-PIM, second-generation SmartSSD), and expanding strategic partnerships to tackle new industry challenges
• Pushing boundaries of logic solutions that can offer enhanced user experiences and new opportunities (5G Exynos Modem, Exynos 2200, 200MP ISOCELL HP3)

Interbrand’s Best Global Brands are listed according to the evaluation of each brand value, which is a result of comprehensive analysis of the financial performance of the company, the influence of the brand on customer purchases and brand competitiveness.

With significant market growth in high-performance computing (HPC), artificial intelligence (AI), 5/6G connectivity and automotive applications, demand for advanced semiconductors has increased dramatically, making innovation in semiconductor process technology critical to the business success of foundry customers. To that end, Samsung highlighted its commitment to bringing its most advanced process technology, 1.4-nanometer (nm), for mass production in 2027.

During the event, Samsung also outlined steps its Foundry Business is taking in order to meet customers’ needs, including: △foundry process technology innovation, △process technology optimization for each specific applications, △stable production capabilities and △customized services for customers.

▲ Dr. Siyoung Choi, president and head of Foundry Business at Samsung Electronics, is giving his keynote speech at Samsung Foundry Forum 2022.

“The technology development goal down to 1.4nm and foundry platforms specialized for each application, together with stable supply through consistent investment are all part of Samsung’s strategies to secure customers’ trust and support their success,” said Dr. Siyoung Choi, president and head of Foundry Business at Samsung Electronics. “Realizing every customer’s innovations with our partners has been at the core of our foundry service.”

Showcasing Samsung’s Advanced Node Roadmap Down to 1.4nm in 2027

With the company’s success of bringing the latest 3nm process technology to mass production, Samsung will be further enhancing gate-all-around (GAA) based technology and plans to introduce the 2nm process in 2025 and 1.4nm process in 2027.

While pioneering process technologies, Samsung is also accelerating the development of 2.5D/3D heterogeneous integration packaging technology to provide a total system solution in foundry services.

Through continuous innovation, its 3D packaging X-Cube with micro-bump interconnection will be ready for mass production in 2024, and bump-less X-Cube will be available in 2026.

▲ Dr. Siyoung Choi, president and head of Foundry Business at Samsung Electronics, is giving his keynote speech at Samsung Foundry Forum 2022.

Proportion of HPC, Automotive and 5G To Be More Than 50% by 2027

Samsung actively plans to target high-performance and low-power semiconductor markets such as HPC, automotive, 5G and the Internet of Things (IoT).

To better meet customers’ needs, customized and tailored process nodes were introduced during this year’s Foundry Forum. Samsung will enhance its GAA-based 3nm process support for HPC and mobile, while further diversifying the 4nm process specialized for HPC and automotive applications.

For automotive customers specifically, Samsung is currently providing embedded non-volatile memory (eNVM) solutions based on 28nm technology. In order to support automotive-grade reliability, the company plans to further expand process nodes by launching 14nm eNVM solutions in 2024 and adding 8nm eNVM in the future. Samsung has been mass producing 8nm RF following 14nm RF, and 5nm RF is currently in development.

‘Shell-First’ Operation Strategy To Respond to Customer Needs in a Timely Manner

Samsung plans to expand its production capacity for the advanced nodes by more than three times by 2027 compared to this year.

Including the new fab under construction in Taylor, Texas, Samsung’s foundry manufacturing lines are currently in five locations: Giheung, Hwaseong and Pyeongtaek in Korea; and Austin and Taylor in the United States.

At the event, Samsung detailed its ‘Shell-First’ strategy for capacity investment, building cleanrooms first irrespective of market conditions. With cleanrooms readily available, fab equipment can be installed later and set up flexibly as needed in line with future demand. Through the new investment strategy, Samsung will be able to better respond to customers’ demands.

Investment plans in a new ‘Shell-First’ manufacturing line in Taylor, following the first line announced last year, as well as potential expansion of Samsung’s global semiconductor production network were also introduced.

Expanding the SAFE Ecosystem To Strengthen Customized Services

Following the ‘Samsung Foundry Forum,’ Samsung will hold the ‘SAFE Forum’ (Samsung Advanced Foundry Ecosystem) on October 4th. New foundry technologies and strategies with ecosystem partners will be introduced encompassing areas such as Electronic Design Automation (EDA), IP, Outsourced Semiconductor Assembly and Test (OSAT), Design Solution Partner (DSP) and the Cloud.

In addition to 70 partner presentations, Samsung Design Platform team leaders will introduce the possibility of applying Samsung’s processes such as Design Technology Co-Optimization for GAA and 2.5D/3DIC.

As of 2022, Samsung provides more than 4,000 IPs with 56 partners, and is also cooperating with nine and 22 partners in the design solution and EDA, respectively. It also offers cloud services with nine partners and packaging services with 10 partners.

Along with its ecosystem partners, Samsung provides integrated services that support solutions from IC design to 2.5D/3D packages.

Through its robust SAFE ecosystem, Samsung plans to identify new fabless customers by strengthening customized services with improved performance, rapid delivery and price competitiveness, while actively attracting new customers such as hyperscalers and start-ups.

Starting in the United States (San Jose) on October 3rd, the ‘Samsung Foundry Forum’ will be sequentially held in Europe (Munich, Germany) on the 7th, Japan (Tokyo) on the 18th and Korea (Seoul) on the 20th, through which customized solutions for each region will be introduced. A recording of the event will be available online from the 21st for those who were unable to attend in person.

Samsung Electronics plans to invest about KRW 20 trillion by 2028 for the complex in an area covering about 109,000 square meters within its Giheung campus. The new facility will lead advanced research on next-generation devices and processes for memory and system semiconductors, as well as development of innovative new technologies based on a long-term roadmap.

Today’s groundbreaking ceremony was attended by Samsung Electronics Vice Chairman Jay Y. Lee, President and CEO Kye Hyun Kyung, President of the Memory Business Jung-Bae Lee, President of the Foundry Business Siyoung Choi and President of the S.LSI Business Yong-In Park, along with more than 100 employees.

“Our new state-of-the-art R&D complex will become a hub for innovation where the best research talent from around the world can come and grow together,” said President Kye Hyun Kyung, who also heads the Device Solutions (DS) Division. “We expect this new beginning will lay the foundation for sustainable growth of our semiconductor business.”

With the establishment of the new R&D facility, Samsung Electronics is seeking to overcome the limits of semiconductor scaling and solidify its competitive edge in semiconductor technology.

Samsung Electronics’ Giheung campus, located south of Seoul near the DS Division’s Hwaseong campus, is the birthplace of the world’s first 64Mb DRAM in 1992, marking the beginning of the company’s semiconductor leadership.

The new Giheung R&D facility, together with the R&D line in Hwaseong and the world’s largest semiconductor production complex in Pyeongtaek, is also expected to elevate the synergy among Samsung’s three main semiconductor complexes in the metropolitan area.

After the ceremony, Vice Chairman Jay Y. Lee visited the Hwaseong campus to meet with employees of the DS Division, where they discussed ways to promote innovation within the company. At a separate meeting with executives of the DS Division, discussions involved current issues in the global semiconductor industry, progress of next-generation semiconductor technology R&D and ways to secure technology to expand semiconductor leadership.

Samsung Electronics has rolled up its sleeves to tackle the marine pollution issue that is threatening the safety of humankind and the environment. The company’s eco-conscious efforts include recycling discarded ocean-bound plastic (OBP) located within 50km of the coast and using recycled materials to produce high-resolution monitors and Galaxy devices.

In addition, the eco-conscious water treatment technology that’s currently being used at the manufacturing sites of Samsung’s Device Solutions (DS) Division significantly reduces water usage, reusing an amount of water equivalent to the total usage of two million people over half a year. Efforts like these underline Samsung’s commitment to conserving water.

Check out the infographic below to learn more about how Samsung is reducing marine pollution by transforming OBP into parts for monitors and mobile devices including smartphones, and by purifying wastewater at its semiconductor plants.

“S3B512C combines a fingerprint sensor, Secure Element (SE) and Secure Processor, adding an extra layer of authentication and security in payment cards,” said Kenny Han, Vice President of System LSI Marketing at Samsung Electronics. “The S3B512C is primarily designed for payment cards but can also be used in cards that require highly secured authentications such as student or employee identification, membership or building access.”

The new security IC is the industry’s first all-in-one security chip solution that reads biometric information through a fingerprint sensor, stores and authenticates encrypted data with a tamper-proof SE, and analyzes and processes data with a Secure Processor. With the three key functions integrated in a single chip, the S3B512C can help card manufacturers reduce the number of chips required and optimize card design processes for biometric payment cards.

With the new security IC embedded, biometric payment cards will allow faster and safer interactions when making purchases. The biometric authentication removes the need to enter a PIN on a keypad and also prevents fraudulent transactions made with lost or stolen cards as it verifies the cardholder’s identity using a unique and securely stored fingerprint.

The solution’s encrypted fingerprint data is stored in a SE that has received globally accredited certifications such as EMVCo and CC EAL 6+. To safely and accurately verify the user’s identity, the new IC comes with a proprietary fingerprint authentication algorithm and a Secure Processor that extracts and analyzes the unique features of the fingerprint placed on the sensor. Furthermore, the chip’s anti-spoofing technology prevents unauthorized users from circumventing the security system with illegitimate methods such as artificial fingerprints.

The new facility will manufacture products based on advanced process technologies for application in areas such as mobile, 5G, high-performance computing (HPC) and artificial intelligence (AI). Samsung remains committed to supporting customers globally by making advanced semiconductor fabrication more accessible and meeting surging demand for leading-edge products.

“As we add a new facility in Taylor, Samsung is laying the groundwork for another important chapter in our future,” said Kinam Kim, Vice Chairman and CEO, Samsung Electronics Device Solutions Division. “With greater manufacturing capacity, we will be able to better serve the needs of our customers and contribute to the stability of the global semiconductor supply chain.”

“We are also proud to be bringing more jobs and supporting the training and talent development for local communities, as Samsung celebrates 25 years of semiconductor manufacturing in the U.S.,” Kim said.

“In addition to our partners in Texas, we are grateful to the Biden Administration for creating an environment that supports companies like Samsung as we work to expand leading-edge semiconductor manufacturing in the U.S.,” continued Kim. “We also thank the administration and Congress for their bipartisan support to swiftly enact federal incentives for domestic chip production and innovation.”

Groundbreaking will be in the first half of 2022 with the target of having the facility operational in the second half of 2024. The Taylor site will span more than 5 million square meters and is expected to serve as a key location for Samsung’s global semiconductor manufacturing capacity along with its latest new production line in Pyeongtaek, South Korea.

The total expected investment of $17 billion, including buildings, property improvements, machinery and equipment, will mark the largest-ever investment made by Samsung in the U.S. This will also bring Samsung’s total investment in the U.S. to more than $47 billion since beginning operations in the country in 1978, where the company now has over 20,000 employees across the country.

“Companies like Samsung continue to invest in Texas because of our world-class business climate and exceptional workforce,” said Governor Abbott. “Samsung’s new semiconductor manufacturing facility in Taylor will bring countless opportunities for hardworking Central Texans and their families and will play a major role in our state’s continued exceptionalism in the semiconductor industry. I look forward to expanding our partnership to keep the Lone Star State a leader in advanced technology and a dynamic economic powerhouse.”

After reviewing multiple locations within the U.S. for a potential manufacturing site, the decision to invest in Taylor was based on multiple factors, including the local semiconductor ecosystem, infrastructure stability, local government support and community development opportunities. In particular, the proximity to Samsung’s current manufacturing site in Austin, about 25 kilometers southwest of Taylor, allows the two locations to share the necessary infrastructure and resources.

This latest expansion of Samsung’s U.S. presence is expected to create over 2,000 high-tech jobs directly and thousands of related jobs once the new facility is in full operation. As part of its co-investment in the community, Samsung will also contribute financial support to create a Samsung Skills Center for the Taylor Independent School District (ISD) to help students develop skills for future careers as well as providing internships and recruiting opportunities.

(left to right) Senator John Cornyn, Governor Greg Abbott, Samsung Electronics Vice Chairman & CEO Kinam Kim

(left to right) Governor Greg Abbott, Samsung Electronics Vice Chairman & CEO Kinam Kim

(left to right) Senator John Cornyn, Governor Greg Abbott, Samsung Electronics Vice Chairman & CEO Kinam Kim

Samsung Electronics, a world leader in advanced semiconductor technology, held its 3^rd Annual Samsung Advanced Foundry Ecosystem (SAFE^TM) Forum 2021 virtually today.

With the theme of ‘Performance Platform 2.0: Innovation, Intelligence, Integration’, Samsung and its foundry ecosystem partners prepared 7 plenary talks and 76 technology sessions focused on three main topics: Gate-All-Around (GAA, Innovation), Artificial Intelligence (AI, Intelligence) and 2.5D/3D (Integration) technologies and the diverse design infrastructures required for high-performance applications.

“In the rapidly changing data-centric era, Samsung and its foundry partners have made great strides responding to increasing customers demand and to support their success by providing powerful solutions,” said Ryan Lee, Senior Vice President and Head of Foundry Design Platform Development at Samsung Electronics. “With the support of our SAFE program, Samsung will lead the realization of the vision ‘Performance Platform 2.0’.”

Starting with a keynote live streaming on November 17, attendees are able to explore a variety of tech sessions and engage with ecosystem partners through the virtual SAFE Forum platform for a month. To register for SAFE forum, please visit https://www.samsungfoundry.com.

SAFE 2021: Performance Platform 2.0

Samsung has concentrated on expanding its foundry ecosystem by focusing on IP, Electronic Design Automation (EDA), Cloud, Design Solution Partner (DSP) and Package solutions necessary for today’s data-driven era. Samsung introduced today its latest SAFE^TM program including:

• SAFE^TM-IP & EDA: Samsung and its foundry ecosystem have reserved over 3,600 IPs and 80 certified EDA tools respectively. These are developed and verified based on the high-standard certification program run by Samsung and participated in by our partners. In order to respond to the demands of high performance applications, Samsung’s foundry ecosystem has developed not only HPC-specific foundation IPs including standard cell libraries and memory compilers but also key IPs, such as over 100Gbps Serializer-Deserializer (SerDes) interface and 2.5D/3D multi-die integration solutions.
  
  With our EDA partners, Samsung has secured design tools optimized for its unique 3-nanometer (nm) GAA process technology and design methodology for integrating multiple dies in 2.5D/3D. Customers can also utilize AI- and machine learning-based EDA technology to systematically manage and analyze design data. To overcome the increasing difficulties of chip design and analysis, Samsung has strengthened cooperation with partners to develop EDA tools and related technologies, such as incorporating GPUs that can efficiently use computing resources required for chip verification.

• SAFE^TM-OSAT: Samsung plans to lead ‘beyond-Moore’ technologies by strengthening various package line-ups such as 2.5D/3D through the expansion of its SAFE-Outsourced Semiconductor Assembly and Test (OSAT) ecosystem. The recent announcement of the co-development of Hybrid-Substrate Cube (H-Cube) solution, which offers efficient integration of 6 HBMs and cost benefit, is one of the successful examples of Samsung foundry’s collaboration with the OSAT community.

• SAFE^TM-Cloud Design Platform: SAFE^TM-CDP, the cloud-based one-stop design platform introduced last year, now supports a hybrid cloud function that can be linked to customers’ conventional design environments.

• SAFE^TM-DSP: Through the SAFE^TM-DSP ecosystem, Samsung and its global partners can actively support global fabless companies to implement their design ideas into custom product by utilizing cutting-edge process technologies as well as high-performance, low-power chip design knowledge.

[Quote from SAFE^TM Partner companies]

• Ansys, Ajei Gopal, CEO

“Today’s chips demand a full multiphysics approach, which requires engineering simulation. Ansys is proud to partner with Samsung to deliver a comprehensive multi-physics analysis flow for Samsung’s multi-die integration initiative. The benefits to joint customers, to the industry – and to the entire world – are tremendous. Semiconductors will drive innovations as varied as autonomous and electric vehicles, artificial intelligence, and mobile technologies, including 5G and beyond.”

• Arm, Simon Segars, CEO

“Our longstanding partnership with Samsung Foundry has been essential for growing business opportunities in many markets for our combined partner ecosystem. This close collaboration continues as we work together to optimize our Armv9 next-generation processors on Samsung Foundry’s leading-edge processes, including GAA, to deliver a best-in-class solution that is optimized for the world of today, and the technologies of tomorrow. Together, we are unlocking new opportunities across HPC, Automotive, AI, and IoT, while also managing rising complexities, enabling faster time to market.”

• Cadence, Lip-Bu Tan, CEO

“The Cadence Intelligent System Design strategy is very well-aligned with Samsung Foundry’s Performance Platform 2.0 with common themes of innovation, pervasive intelligence and integrated solutions. Together, we’re enabling customers to develop and deliver innovative, breakthrough products using Samsung’s most advanced process and packaging technologies, and we look forward to continuing our work with Samsung Foundry to accelerate design successes”

• Siemens EDA, A. J. Incorvaia, Senior Vice President

“The Samsung SAFE event provides an exceptionally valuable venue for the Samsung Foundry ecosystem to meet, share information and identify opportunities to fully leverage Samsung’s cutting-edge process technologies. Siemens EDA looks forward to this year’s Samsung SAFE event and the many opportunities it presents for collaborating with customers and partners to eliminate design obstacles and enhance silicon success.”

• Synopsys, Sassine Ghazi, president and COO

“We see exciting times ahead as software and chip technology come together to create world-changing new products,” said Sassine Ghazi, president and COO of Synopsys. “We have strong programs with Samsung Foundry on 3nm gate-all-around enablement, broad IP certification, AI-assisted chip design and 2.5/3D multi-die design to name just a few. We welcome the strong collaboration opportunities offered by the Samsung SAFE initiative.”

Samsung Electronics, a world leader in advanced semiconductor technology, today unveiled plans for continuous process technology migration to 3- and 2-nanometer (nm) based on the company’s Gate-All-Around (GAA) transistor structure at its 5^th annual Samsung Foundry Forum (SFF) 2021.

With a theme of Adding One More Dimension, the multi-day virtual event is expected to draw over 2,000 global customers and partners. At this year’s event, Samsung will share its vision to bolster its leadership in the rapidly evolving foundry market by taking each respective part of foundry business to the next level: process technology, manufacturing operations and foundry services.

“We will increase our overall production capacity and lead the most advanced technologies while taking silicon scaling a step further and continuing technological innovation by application,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics.” Amid further digitalization prompted by the COVID-19 pandemic, our customers and partners will discover the limitless potential of silicon implementation for delivering the right technology at the right time.”

GAA Is Ready for Customers’ Adoption – 3nm MP in 2022, 2nm in 2025

With its enhanced power, performance and flexible design capability, Samsung’s unique GAA technology, Multi-Bridge-Channel FET (MBCFET^TM), is essential for continuing process migration. Samsung’s first 3nm GAA process node utilizing MBCFET will allow up to 35 percent decrease in area, 30 percent higher performance or 50 percent lower power consumption compared to the 5nm process. In addition to power, performance and area (PPA) improvements, as its process maturity has increased, 3nm’s logic yield is approaching a similar level to the 4nm process, which is currently in mass production.

Samsung is scheduled to start producing its customers’ first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023. Newly added to Samsung’s technology roadmap, the 2nm process node with MBCFET is in the early stages of development with mass production in 2025.

FinFET for CIS, DDI, MCU – 17nm Specialty Process Technology Debuts

Samsung Foundry is continuously improving its FinFET process technology to support specialty products with cost-effective and application-specific competitiveness. A good example of this is the company’s 17nm FinFET process node. In addition to the intrinsic benefits afforded by FinFET, the process node has excellent performance and power efficiency leveraging a 3D transistor architecture. Consequently, Samsung’s 17nm FinFET provides up to 43 percent decrease in area, 39 percent higher performance or a 49 percent increase in power efficiency compared to the 28nm process.

Additionally, Samsung is advancing its 14nm process in order to support 3.3V high voltage or flash-type embedded MRAM (eMRAM) which enables increased write speed and density. It will be a great option for applications such as micro controller units (MCUs), IoT and wearables. Samsung’s 8nm radio frequency (RF) platform is expected to expand the company’s leadership in the 5G semiconductor market from sub-6GHz to mmWave applications.

Looking ahead, in cooperation with its ecosystem partners, Samsung Foundry’s SAFE Forum will be held virtually in November 2021.

Samsung Newsroom invites you to take a tour of these five Korea-based manufacturing centers in the video below, captured via drone for an amazing birds-eye look at the innovative campuses. Check out the video below to learn more.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced that it received the industry’s first Triple Standard for carbon, water and waste by Carbon Trust.

Samsung was awarded this certification by reducing the amount of carbon emissions, water use, and waste discharge over the past three years at five operations (Giheung, Hwaseong, Pyeongtaek, Onyang and Cheonan) in Korea and four global manufacturing sites in U.S. and China (Austin, Suzhou, Tianjin and Xi’an). This is a huge feat, considering that it is extremely challenging for semiconductor manufacturing companies to meet all three qualifications at once.

“For decades, Samsung has been striving to incorporate environmental sustainability into every aspect of the semiconductor manufacturing process,” said Seong-dai Jang, senior vice president and head of DS Corporate Sustainability Management Office at Samsung Electronics. “We’ll continue to pursue more environmentally sustainable policies across the entire production and supply chain.”

Samsung has been making various efforts in carbon reduction, water resource conservation and recycling, and has been managing these as important sustainability goals.

Samsung’s Efforts to Reduce Its Environmental Footprint

• Greenhouse Gas: Samsung has been sourcing 100-percent renewable energy for its overseas semiconductor operations in the United States and China since 2019, and the company’s continued efforts to reduce its carbon footprint also includes optimizing gas use for etching and deposition processes, as well as developing new catalysts for its greenhouse gas reduction equipment. Through these endeavors, Samsung was able to cut about 1.3-million tons¹ of carbon emissions in 2020—about 200 million pine trees would be required to absorb the same amount of carbon.²
• Water Management: Samsung has been recycling wastewater generated in the process of producing ultra-pure water for equipment such as wet scrubbers and cooling towers. The company has also reduced water usage utilizing its wastewater filtration technology—known as the ‘membrane process’ —to reuse water and optimize manufacturing processes. Equipment operation efficiency has also increased by consolidating wastewater reclamation and reuse systems. As a result, Samsung was able to reuse about 70 million tons of water in 2020, a 12-percent increase compared to 2018~2019, and reduce more than 10 million tons of water usage,³ which is the same amount used for two-million people per month in a metropolitan area in Korea.⁴
• Waste Discharge: Samsung has significantly reduced wastewater sludge,⁵ which accounts for more than 60-percent of total waste generation, by applying alternative materials and optimizing the amount of materials supplied to particular facilities. In addition, by establishing packaging standards for products brought into the line, the amount of waste from over-packaging has also been reduced. Through all these efforts, Samsung reduced a total of 35,752 tons⁶ of waste discharged in 2020.

Samsung Electronics strives to incorporate environmental sustainability into everything it does. Samsung’s products are thoughtfully designed to minimize the impact on the environment during their entire lifecycle – from planning and manufacturing to consumption and recycling.

¹ The amounts stated are converted measurements based on production levels

² A 30-year-old pine tree can absorb about 6.6 kilograms of carbon dioxide (CO2) per year (Korea Institute of Forest Science)

³ The amounts stated are converted measurements based on production levels

⁴ Korea Ministry of Environment (2019)

⁵ Wastewater sludge is a by-product generated in the treatment process of industrial wastewater or sewage.

⁶ The amounts stated are converted measurements based on production levels

Samsung Electronics, a world leader in advanced semiconductor technology, today announced the industry’s first integrated power management ICs (PMICs) — S2FPD01, S2FPD02 and S2FPC01, for the fifth-generation double data rate (DDR5) dual in-line memory module (DIMM).

One major design improvement to the newest generation DRAM solution involves integrating the PMIC into the memory module — previous generations placed the PMIC on the motherboard — offering increased compatibility and signal integrity, and providing a more reliable and sustained performance.

For improved performance efficiency and load-transient responses, Samsung’s new PMICs for DDR5 modules have been equipped with a high-efficiency hybrid gate driver and a proprietary control design (asynchronous-based dual-phase buck control scheme).

This scheme allows the DC voltage to step down from high to low with a fast transient response to changes in the output load current and adapts the conversion accordingly to efficiently regulate its output voltage at near-constant levels. The control scheme also features both pulse width and pulse frequency modulation methods, preventing delays and malfunctions when switching modes.

“With enhanced power efficiency and low output ripple voltage, the new PMICs S2FPD01, S2FPD02 and S2FPC01 allow data centers, enterprise servers and PC applications to take full advantage of their DDR5 performance for highly demanding, memory-intensive tasks,” said Harry Cho, vice president of System LSI marketing at Samsung Electronics.

Two of Samsung’s new DDR5 DIMM PMIC solutions, the S2FPD01 and the S2FPD02, offer optimal performance for today’s data center and enterprise servers that must run heavy analytics, machine and deep learning, and other various computing tasks in real time. The FPD01 is designed for modules with low density; FPD02 for higher density.

In addition, by implementing a high-efficiency hybrid gate driver instead of a linear regulator, Samsung’s new PMICs can operate at up to 91-percent power efficiency.

The S2FPC01, Samsung’s other new PMIC, is tailored for use in desktop or laptop PCs. Designed on a 90-nanometer (nm) process node, the PMIC solution offers a more agile performance in a smaller package.

Samsung’s DDR5 DIMM power management ICs, the S2FPD01, S2FPD02 and S2FPC01, are currently being sampled to customers.

The plan represents an increase of KRW 38 trillion from the previous commitment of KRW 133 trillion announced in April 2019 and is expected to help the Company reach its goal of becoming the world leader in logic chips by 2030. For the past two years, Samsung has been closely collaborating with various semiconductor design companies, component and equipment manufacturers, as well as academia in making progress towards that goal.

The expansion of the Company’s Foundry Business will help fuel entire new industries built on next-generation technologies like AI, 5G and autonomous driving.

The Company also announced that it has begun construction of a new production line in Pyeongtaek, Korea, which is expected to be completed in the second half of 2022. The state-of-the-art facility equipped with the latest technology, P3, will produce 14-nanometer DRAM and 5-nanometer logic semiconductors, both based on extreme ultraviolet (EUV) lithography technology.

“The entire semiconductor industry is facing a watershed moment and now is the time to chart out a plan for long-term strategy and investment,” said Dr. Kinam Kim, Vice Chairman and Head of Device Solutions Division at Samsung Electronics. “For the memory business, where Samsung has maintained its undisputed leadership position, the Company will continue to make preemptive investments to lead the industry.”

As one of the world’s largest semiconductor clusters, Pyeongtaek will serve as the leading hub for next-generation innovations.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced the immediate availability of its next-generation 2.5D packaging technology Interposer-Cube4 (I-Cube4), leading the evolution of chip packaging technology once again.

Samsung’s I-Cube^TM is a heterogeneous integration technology that horizontally places one or more logic dies (CPU, GPU, etc.) and several High Bandwidth Memory (HBM) dies on top of a silicon interposer, making multiple dies operate as a single chip in one package.

Samsung’s new I-Cube4, which incorporates four HBMs and one logic die, was developed in March as the successor of I-Cube2. From high-performance computing (HPC) to AI, 5G, cloud and large data center applications, I-Cube4 is expected to bring another level of fast communication and power efficiency between logic and memory through heterogeneous integration.

“With the explosion of high-performance applications, it is essential to provide a total foundry solution with heterogeneous integration technology to improve the overall performance and power efficiency of chips,” said Moonsoo Kang, senior vice president of Foundry Market Strategy at Samsung Electronics. “With the mass-production experience amassed through I-Cube2 and the commercial breakthroughs of I-Cube4, Samsung will wholly support customers’ product implementations.”

In general, the silicon interposer area proportionally increases to accommodate more logic dies and HBMs. Since the silicon interposer in the I-Cube is thinner (around 100㎛ thick) than paper, the chances of bending or warping a larger interposer become higher, which negatively impacts product quality.

With strong expertise and knowledge on semiconductors, Samsung has studied how to control interposer warpage and thermal expansion through changes to material and thickness, succeeding in commercializing the I-Cube4 solution.

Additionally, Samsung has developed its own mold-free structure for I-Cube4 to efficiently remove heat and enhanced its yield by conducting a pre-screening test that can filter out defective products during the fabrication process. This approach provides additional benefits such as a reduction in the number of process steps, which result in cost savings and shorter turnaround time.

Since the launch of I-Cube2 in 2018 and eXtended-Cube (X-Cube) in 2020, Samsung’s heterogeneous integration technology has signaled a new era in the high-performance computing market. Samsung is currently developing more advanced packaging technologies to I-Cube6 and higher by using a combination of advanced process nodes, high speed interface IPs and advanced 2.5/3D packaging technologies, which will help customers design their products in the most effective way.

I-Cube4TM (Interposer Cube) Package Structure

▲(From left) The Samsung developers who built the integrated circuits in the company’s 8K TVs – Sangdeok Kim, Hansoo Seong, Junghyun Lim, and Yongjoo Song

With the continued evolution of high-definition televisions, the worlds displayed on our TV screens are becoming more realistic than ever. 8K TVs, which represent the new standard of premium television, maximize immersion by providing such vivid high definition that it is like users are beholding the scenes before their very eyes.

This incredibly sharp resolution was made possible by the enhancement of the semiconductors within the TVs. Capable of enabling the functions that allow sharper resolution, these solutions are the DTV SoC (Digital TV System on Chip), T-CON (Timing Controller), and DDI (Display Driver IC). Samsung Newsroom sat down with the developers of S6HD820 (which opened the door for 8nm¹ DTV SoC), S6TST21 (the industry’s first 8K 120Hz T-CON) and S6CT9BC (a DDI with a maximum speed of 8Gbps) to hear the story of the unseen innovation behind these solutions.

From DTV SoC to DDI – Sending Video Signals to Displays

Unlike in the past when televisions were only used for watching shows, the role of the TV has gradually expanded over time. These days, our TVs are becoming a platform that also allows us to play games, work out as well as do a broad range of other activities. As people come to expect a more diverse range of features from their TVs, a higher standard of premium features is also being brought to televisions.

TVs are output devices for content, making a high standard of picture quality crucial for user satisfaction. Digital signals generally undergo three stages before being displayed. First, the DTV SoC receives compressed data from broadcasts or the internet, extracts the data to convert it into video and sends the video and audio to the screen and speakers. The T-CON then receives the processed video data and sends it back to the DDI with careful timing to ensure smooth operation. Last, the digital signal sent to the DDI is converted to an analog format and the video is displayed on the TV screen.

Simplifying DTV SoC With ‘One Chip’ and Enhancing NPU Function

The DTV SoC, which receives video data from a cable or set-top box, is also referred to as ‘the brain of the TV.’ Hansoo Seong, who is part of the DTV SoC development team, explains that, “The DTV SoC extracts the audio and video signals separately from the compressed input stream. It then provides the function that adjusts the audio and video data according to each scene being displayed.”

As picture quality has evolved from the 4K to the 8K standard, the role of the DTV SOC has become more important. Samsung’s developers were committed to finding a solution that would support 8K resolution while also reducing power usage at the same time. An NPU (Neural Processing Unit) was applied to the DTV SoC so that AI technology could be applied to the overall improvement of both picture quality and audio processing. This technology led to a much more precise display output. On top of this, the DTV SoC has been integrated with an upscaling IC² to improve power efficiency.

The biggest hurdle in creating the 8nm¹ DTV SoC, known as S6HD820, was the complex engineering required to integrate two ICs into one chip and the subsequent issue of overheating. “The better the NPU performance, the more the AI learning is reinforced, which leads to better TV performance. But this also makes semiconductors that much more complex to engineer and results in more severe overheating,” said Hansoo Seong. “We worked hard to find the right balance to prevent excessive overheating, and eventually succeeded in optimizing the solution.”

The Evolution of T-CON: From Two 60Hz Chips to a Single 120Hz Chip

The T-CON takes the video data from the DTV SoC and converts it according to the demands of the DDI. “The bigger the panel size and the higher the resolution, the more important the role of the T-CON becomes,” said Junghyun Lim, who participated in developing Samsung’s latest 8K T-CON. “The data transmission speed of the T-CON is also important when it comes to quickly transmitting high-resolution video data to the DDI.”

With the improvement from 4K to 8K, screen resolution increases by four times. Thus, the amount of data that needs to be sent also quadruples, which means the T-CON’s speed needs to be enhanced as well. The development team solved the overheating problem that accompanies rapidly rising speeds by applying a new node process and simplifying the chips. In addition, the two 8K 60Hz chips have been integrated to become one S6TST21.

Previous systems required four semiconductors in 8K TVs, including the DTV SoC, the upscaling IC² for 8K, and two T-CONs. The new system has reduced the total amount of semiconductors required to two by combining the DTV SOC and the upscaling IC² into one solution, and merging the two T-CONs into one. These changes have made it much easier to design the required boards.

DDI Integration Increases Speeds and Reduces Chip Count

The DDI is responsible for the final step before the video is displayed. This is where the digital data received from the T-CON is converted into the analog signal that will be used as input for the display. Yongjoo Song, who participated in development of the DDI, said, “The DDI needs to deliver high analog voltage to the panel quickly and precisely to allow the video data from the T-CON to be displayed accurately.”

To facilitate the increase in voltage, a new driver IC became necessary that could simultaneously handle higher voltages and prevent overheating. “Increasing the speed of the driver buffer was the most difficult challenge,” said Yongjoo Song. “After changing the circuit structure and layout in a range of ways to reduce the driver IC’s input/output latency, we were able to develop a new driver IC that could operate at faster speeds.”

The development of a DDI that operates at high speeds resulted in the number of DDIs being reduced by almost half and the number of relevant chips being reduced by dozens. This makes TV panels easier to construct.

The Secret to Tech Leadership: Development of Samsung’s Own Interface and Organic Semiconductor

From 4K to 8K TVs, the secret to Samsung’s technological leadership is its know-how and the high level of consumer trust it has accumulated over time. In addition, Samsung is constantly analyzing market and technology trends to apply them to products, and Samsung’s own interface has played a huge role in these efforts. “The Samsung interface not only delivers speed but also utilizes the company’s semiconductor driver technologies,” said Sangdeok Kim. “By utilizing its own interface, Samsung was able to make the 8K TV DDI based on the industry’s fastest interface.”

Another one of Samsung’s unique advantages is that it is developing the DTV SoC, T-CON and DDI in tandem with one another. This offers a big advantage, as it allows better integration and compatibility among the three components that must work together.

The developers from Samsung’s S.LSI Business make no secret of their excitement regarding 8K TV technology and the future of semiconductors. “When I first started working in this area, I was making semiconductors for FHD-resolution TVs. I remember feeling very proud when the products entered mass production,” related Yongjoo Song. “Already, TV resolutions have surpassed 4K to reach the 8K standard, and TV screens continue to get bigger and bigger. With larger high-resolution TVs being introduced to the market, semiconductors must be equipped to perform more complex functions, which adds to the challenges in developing them. But overcoming those challenges will remain the ever-present goal for developers like us.”

¹ nm: nanometer

² Upscaling IC: A semiconductor that converts low-resolution videos into high resolution (converts 2K and 4K videos into 8K)

A transistor is a semiconductor device used to transform the digital information coded in the binary system into electric signals. A transistor is composed of a ‘channel’ in which the electric current flows between the semiconductor’s source and its drain and a ‘gate’ for managing the electric current traveling through the channel. The gate generates binary system data by amplifying electric signals and also working as a switch. Because of this, the transistor is essentially the basic element of a semiconductor chip.

All digital information, be it in the form documents, photos or videos, is in fact a composed of the binary numeral system, which only uses two symbols, ‘0’ and ‘1’.

In order to increase the number of semiconductor chips mounted on the limited surface of a silicon (Si) substrate, the size of each semiconductor chip naturally needs to be decreased. Furthermore, in order to fit more new and complex functions into each semiconductor chip, the very basic element transistor must become smaller and its power consumption must be minimized to provide the longest possible battery lifespan, as well as reduced heat and electric charges. As electricity consumption is dependent on operating voltage, transistors have been developed so as to decrease operating voltage. Therefore, the history of the semiconductor is synonymous with the history of creating transistors that are smaller, faster and that consume less electricity.

The history of the development of the semiconductor is synonymous with the history of creating transistors that are smaller, faster and that consume less electricity. From the left, Planar Transistor, Fully Depleted (Fin) Transistor, and GAA Transistor

The most widely used transistor in the current semiconductor industry is the Metal-Oxide-Semiconductor (MOS). It consists of a metal electrode, an oxide insulator and a semiconductor channel. The first MOS transistor was of a planar architecture and was structured so that the gate and the channel made contact on one plane. But, as transistors become smaller, the distance between the source and the drain gets smaller, making it difficult for the gates to work as a switch. This is called a ‘short-channel effect’, and along with limiting voltage reduction, it means that planar transistors can only be applied to 20 or above nanometer nodes (or generations)¹.

In order to overcome the short-channel effect, the Fully Depleted transistor emerged as the next generation of transistor. This transistor uses a thin silicon (Si) channel to avoid the short-channel effect by enhancing the ability of the gate to adjust the channel. Its structure format evolved out of that of the conventional transistor (a gate on a plane channel) to become a thin, rugged structure with a standing rectangular channel that interlocks with gates on three sides. As this thin, standing channel somewhat resembles a fish’s dorsal fin, it is also called the ‘fin transistor’. Samsung has been manufacturing fin transistors since 2012 in a range of sizes, starting at just 14 nanometers.

Whereas a planar transistor only allows the channel and the gate to contact in just one plane, a fin transistor has a 3-dimensional structure that allows three sides of a channel (excluding its bottom) to come into contact with the gates. This increased contact with the gates improves semiconductor performance as well as increasing the reduction of operating voltage, solving the problems brought about by the short-channel effect.

Nevertheless, the fin transistor is now facing limitations after several generations of developments and process transitions. Nowadays, the semiconductor industry is increasingly requiring transistors that can reduce operating voltage even further. Despite the fin transistor’s 3-dimensional structure, that only three of the four sides are in contact with gates is now becoming a limitation, as transistors themselves continue to progress and subsequently get smaller.

The evolution of semiconductor transistors

In order to mitigate the limitations of existing transistors solutions, Samsung has developed a new structure, the Gate-All-Around (GAA). As the name suggests, the GAA is a structure that maximizes gates’ channel-controlling function, as all channels, including the fourth bottom one, are covered by gates. The gates provide a 360-degree coverage of the entire channel area to eliminate the short-channel effect, resulting in reducing operating voltage further.

A typical GAA transistor takes the form of a thin and long nanowire². However, a channel needs to be as wide as possible in order to allow a large amount of current to flow through it, and the small diameter of the nanowire makes obtaining this higher current flow difficult. To overcome this, Samsung created and patented their proprietary MBCFET (Multi-Bridge Channel Field Effect Transistor), an optimized version of the GAA transistor. The MBCFET increases the areas that make contact with gates by aligning wire-formed channel structures as a 2-dimensional nanosheets, which enables simpler device integration as well as increasing the electric current. Samsung’s MBCFET is a competitive transistor structure in that it not only includes the means to mitigate the short-channel effect thanks to the GAA structure, but it also increases performance by expanding the channel area.

Compared to existing 7-nanometer fin transistor process technology, the MBCFET decreases power consumption by 50%, improves performance by 30%, and reduces the area that the transistor takes up by 45%.

The development of GAA transistors, tantamount to the Industrial Revolution of semiconductor technology, is such a difficult process that Samsung is the only company currently offering a future delivery plan. Furthermore, the successful creation of the MBCFET is indicative of Samsung’s global industry-leading technological prowess. It has laid the foundation for transforming the semiconductor industry that was set to stall at the 4-nanometer scale, along with providing core technologies necessary for bringing about the fourth industrial revolution.

With this latest market-leading development, Samsung is paving the way for the future of the industry thanks to its collaborative approach and trailblazing technologies.

As a semiconductor engineer working in an industry that is entering an era of transformation brought about by new technology, I am very excited to see what the future holds.

¹Nanometer is a measurement for a semiconductor. 1 nanometer is equal to one billionth of a meter.

²An ultra-tiny line that has one nanometer in section diameter