The “Beyond Moore” Era: Pushing the Boundaries of Semiconductors

In the past, the technological advancement in the world of semiconductors revolved around who could make smaller transistors and fit more on a single chip. Gordon Moore predicted that the density of transistors on a chip doubles every 24 months — the famous “Moore’s Law”. Although it has gone through some adjustments over history to reflect the speed of technological growth, “Moore’s Law” has been considered the fundamental principle of semiconductor technology development for the last five decades.

Today’s era of smartphones, mobile internet, AI and big data calls for increasingly faster speeds of computing performance. However, the speed of semiconductor innovation and technology advancement has slowed down, and chip miniaturization has reached physical limits, which has caused the speed at which transistors are growing smaller to slow down. In other words, we are now falling behind Moore’s Law.

The market also demands semiconductors to be versatile, encompassing a variety of features such as analog or RF wireless communication in one chip. But as the semiconductor process becomes increasingly miniaturized, it gets increasingly difficult to maintain analog performance. It is indeed becoming difficult to address the needs of the market just through process miniaturization based on Moore’s Law.

In order to overcome these limitations of semiconductor technology, an approach that goes beyond the existing Moore’s Law is required, and we call this “Beyond Moore”.

“Advanced Package, Leading the Beyond Moore Era”

Our answer to the Beyond Moore era is Advanced Package technology. Through advanced Heterogeneous Integration, which connects multiple chips horizontally and vertically, more transistors can be planted on a single chip (or package) and offer performance that is more powerful than the sum of all parts.

According to market research, the CAGR of the advanced packaging industry is estimated at 9.6% growth rate between 2021 and 2027. In fact, 2.5D¹ and 3D packages² implementing heterogeneous integration is expected to show an even higher growth rate of 14%.

Governments are also paying close attention. The South Korean Ministry of Trade, Industry and Energy hosted a forum on semiconductor packaging technology in February, while DARPA (Defense Advanced Research Projects Agency) of the US Department of Defense announced the allocation of a large-scale budget for advanced package-related fields last April. The Japanese government also announced new incentives to attract research centers, as well as establishing a dedicated symposium.

“One-Stop Advanced Package Solution with High Performance and Low Power”

In a bid to address the growing importance of advanced packaging technology, Samsung Electronics established the AVP (AdVanced Package) Business Team under the Device Solutions Division last December to boost the company’s capabilities in advanced packaging technology and maximize the synergy between business units.

Samsung Electronics, with industry-leading expertise in memory, logic foundry and package business, is well-positioned to utilize heterogeneous integration to offer competitive 2.5D and 3D packages that connect state-of-the-art logic semiconductors produced with EUV and high-performance memory semiconductors such as HBM.

The AVP Business Team operates under a business model that provides one-stop advanced package solutions that enable high-performance and low-power solutions. We communicate closely and directly with customers in order to provide solutions tailored to the needs of each customer and product. Our focus areas are the development of next-generation 2.5D and 3D advanced package solutions based on RDL,³ Si Interposer/Bridge⁴ and TSV⁵ stacking technologies.

“Our Future Beyond Connection”

The goal of the AVP Business Team is “hyper-connection” (or “hyper-integration”). “Hyper-connection” is more than a simple sum of the performance and functions of each semiconductor. We envision creating a greater synergy that connects semiconductors to the world, connects people to people and connects customers’ imaginations to reality.

Samsung Electronics is committed to a competitive development and production strategy, with proprietary packaging technology compatible with the large-area trend. Based on customer-oriented business development that ensures prompt responses to customer requests, the AVP Business Team will bring products of imagination to reality.

¹ 2.5D package: A package which integrates a single-layer logic semiconductor and multi-layer memory semiconductor together on a substrate
² 3D package: a package in which multiple logic/memory semiconductors are vertically integrated
³ RDL (Redistribution Layer): Advanced packaging technology that places an extra metal layer in between a small and large circuit board to integrate the two
⁴ Si Interposer/Bridge: The microcircuit board inserted between the IC chip and PCB, which physically connects the chip and board by acting as the mid-level wiring
⁵ TSV (Through Silicon Via): Advanced package technology that grinds the surface of the chip, drills hundreds of microscopic holes and connects the electrodes that vertically penetrate the holes in the top and bottom chips.

This breakthrough was made possible by combining 32 of the new 1TB NAND flash packages, each comprised of 16 stacked layers of 512Gb V-NAND chips. These super-dense 1TB packages allow for approximately 5,700 5-gigabyte (GB), full HD movie files to be stored within a mere 2.5-inch storage device.

In addition to the doubled capacity, performance levels have risen significantly and are nearly twice that of Samsung’s previous generation high-capacity SAS SSD. Based on a 12Gb/s SAS interface, the new PM1643 drive features random read and write speeds of up to 400,000 IOPS and 50,000 IOPS, and sequential read and write speeds of up to 2,100MB/s and 1,700 MB/s, respectively. These represent approximately four times the random read performance and three times the sequential read performance of a typical 2.5-inch SATA SSD*.

“With our launch of the 30.72TB SSD, we are once again shattering the enterprise storage capacity barrier, and in the process, opening up new horizons for ultra-high capacity storage systems worldwide,” said Jaesoo Han, executive vice president, Memory Sales & Marketing Team at Samsung Electronics. “Samsung will continue to move aggressively in meeting the shifting demand toward SSDs over 10TB and at the same time, accelerating adoption of our trail-blazing storage solutions in a new age of enterprise systems.”

Samsung reached the new capacity and performance enhancements through several technology progressions in the design of its controller, DRAM packaging and associated software. Included in these advancements is a highly efficient controller architecture that integrates nine controllers from the previous high-capacity SSD lineup into a single package, enabling a greater amount of space within the SSD to be used for storage. The PM1643 drive also applies Through Silicon Via (TSV) technology to interconnect 8Gb DDR4 chips, creating 10 4GB TSV DRAM packages, totaling 40GB of DRAM. This marks the first time that TSV-applied DRAM has been used in an SSD.

Complementing the SSD’s hardware ingenuity is enhanced software that supports metadata protection as well as data retention and recovery from sudden power failures, and an error correction code (ECC) algorithm to ensure high reliability and minimal storage maintenance. Furthermore, the SSD provides a robust endurance level of one full drive write per day (DWPD), which translates into writing 30.72TB of data every day over the five-year warranty period without failure. The PM1643 also offers a mean time between failures (MTBF) of two million hours.

Samsung started manufacturing initial quantities of the 30.72TB SSDs in January and plans to expand the lineup later this year – with 15.36TB, 7.68TB, 3.84TB, 1.92TB, 960GB and 800GB versions – to further drive the growth of all-flash-arrays and accelerate the transition from hard disk drives (HDDs) to SSDs in the enterprise market. The wide range of models and much improved performance will be pivotal in meeting the growing storage needs in a host of market segments, including the government, financial services, healthcare, education, oil & gas, pharmaceutical, social media, business services, retail and communications sectors.

* Compared to 2.5-inch Samsung SSD 850 EVO

The industry’s solution to the dilemma was to adopt three dimensional concepts to semiconductor structures at several different stages of the engineering process, hence ‘3D semiconductor technologies.’

Here are some of the key ‘3D technologies’ that Samsung has introduced to the semiconductor industry, and how they tackled important technical challenges in meeting the market requirements.

14-nanometer FinFET

While conventional 2D transistors started to show several problems, including current leakage (a.k.a. short channel effect) that comes with finer technologies, the 14-nanometer (nm) FinFET technology raises a ‘fin’ that wraps over the conducting channel. This allows better control of the current in finer circuit designs. The new structure significantly decreases data leakage while demonstrating greater power advantages.

Samsung made this cutting-edge technology available at the end of 2014 which has enhanced hardware design and performance in today’s premium mobile devices.

Vertical NAND (V-NAND)

Advanced NAND flash technology at smaller design nodes started to experience issues with performance and durability, including data crosstalk.

In 2013, Samsung reached a breakthrough by mass producing V-NAND memory, which vertically stacks the cells with 3D Charge Trap Flash structures, which drastically increases density with less energy consumption and enhanced endurance. Samsung is currently mass producing its third-generation V-NAND lineup.

TSV (Through Silicon Via)

Instead of the traditional method of connecting the stacked dies externally with gold wire, we are now able to pierce hundreds of fine holes through the dies and then vertically connect them through the holes, allowing faster data processing with less power consumed. This technology is called 3D Through Silicon Via, or TSV.

Early this year, Samsung started mass producing the industry’s fastest DRAM package (4GB) based on the High Bandwidth Memory 2 (HBM2) interface. The state-of-the-art technology allows next-generation High Performance Computing systems and graphics cards brought to life.

“By mass producing next-generation HBM2 DRAM, we can contribute much more to the rapid adoption of next-generation HPC systems by global IT companies,” said Sewon Chun, senior vice president, Memory Marketing, Samsung Electronics. “Also, in using our 3D memory technology here, we can more proactively cope with the multifaceted needs of global IT, while at the same time strengthening the foundation for future growth of the DRAM market.”

The newly introduced 4GB HBM2 DRAM, which uses Samsung’s most efficient 20-nanometer process technology and advanced HBM chip design, satisfies the need for high performance, energy efficiency, reliability and small dimensions making it well suited  for next-generation HPC systems and graphics cards.

Following Samsung’s introduction of a 128GB 3D TSV DDR4 registered dual inline memory module (RDIMM) last October, the new HBM2 DRAM marks the latest milestone in TSV (Through Silicon Via) DRAM technology.

The 4GB HBM2 package is created by stacking a buffer die at the bottom and four 8-gigabit (Gb) core dies on top. These are then vertically interconnected by TSV holes and microbumps. A single 8Gb HBM2 die contains over 5,000 TSV holes, which is more than 36 times that of a 8Gb TSV DDR4 die, offering a dramatic improvement in data transmission performance compared to typical wire-bonding based packages.

Samsung’s new DRAM package features 256GBps of bandwidth, which is double that of a HBM1 DRAM package. This is equivalent to a more than seven-fold increase over the 36GBps bandwidth of a 4Gb GDDR5 DRAM chip, which has the fastest data speed per pin (9Gbps) among currently manufactured DRAM chips. Samsung’s 4GB HBM2 also enables enhanced power efficiency by doubling the bandwidth per watt over a 4Gb-GDDR5-based solution, and embeds ECC (error-correcting code) functionality to offer high reliability.

In addition, Samsung plans to produce an 8GB HBM2 DRAM package within this year. By specifying 8GB HBM2 DRAM in graphics cards, designers will be able to enjoy a space savings of more than 95 percent, compared to using GDDR5 DRAM, offering more optimal solutions for compact devices that require high-level graphics computing capabilities.

The company will steadily increase production volume of its HBM2 DRAM over the remainder of the year to meet anticipated growth in market demand for network systems and servers. Samsung will also expand its line-up of HBM2 DRAM solutions to stay ahead in the high-performance computing market and extend its lead in premium memory production.

Current technology trends, including the ever-growing mobile traffic, high-quality content, data analyses and IoT platforms all add to the workload of today’s data centers and servers. As such, faster and more reliable memory solutions with heavy-duty capacities are a necessity.

Chip stacking for larger capacities does have clear benefits. However, with conventional packaging techniques that use wire bonding, chip stacks are prone to lag in speed—speed that is especially essential for enterprise servers that handle massive amounts of data. In turn, dies can only be stacked so high, further limiting the chip package capacity.

Through silicon via (TSV) is an advanced chip packaging technology that vertically connects DRAM chip dies using electrodes that penetrate the microns-thick dies through microscopic holes.
The technology marks a breakthrough from traditional wire bonding as it allows for all of the dies in a chip package to maintain their optimum performance which makes higher die stacks possible. A smaller footprint of the physical chip package is an additional bonus.

Samsung announced its TSV DDR4 DRAM in 128GB RDIMM modules for the first time in the industry, which will bring new heights to memory solutions for servers and data centers.

The three most important benefits of this new technology include:

1. Largest Capacity: Samsung’s 128GB TSV DDR4 module doubles the largest capacity of previous DRAM for enterprise servers while continuing to meet the requirements for high speed and reliability.
2. Faster Speeds: By combining TSV technology with 8Gb DRAM die, Samsung’s new TSV DDR4 RDIMM is able to pack in 128GB, meeting the needs of today’s enterprise servers with speeds of up to 2,667 megabits per second (Mbps) and 3,200Mbps. This suggests the possibility of accelerated adoption of TSV in the market, with opportunities for expanded applications in high bandwidth memory (HBM) and consumer products in the future.
3. Better Efficiency: The design of the 128GB TSV DDR4 module is also incredibly innovative. Traditional wire-bond dies are packaged together with a data buffer chip, which regulate the input/output information passing through each DRAM. Samsung’s new 128GB TSV DDR4 module embeds data buffer functions within the master chip in each chip package, producing better performance in a more energy-efficient product. Being manufactured with Samsung’s state-of-the-art 20-nanometer process technology adds to improved performance and energy efficiency, as well. As a result, the 128GB TSV DDR4 reduces the power consumption by half when compared to the previous highest capacity DRAM modules (64GB LRDIMM).

Read more:

Samsung Starts Mass Producing Industry’s First 128-Gigabyte DDR4 Modules for Enterprise Servers

Samsung Electronics announced that it is mass producing the industry’s first “through silicon via” (TSV) double data rate-4 (DDR4) memory in 128-gigabyte (GB) modules, for enterprise servers and data centers.

Following Samsung’s introduction of the world-first 3D TSV DDR4 DRAM (64GB) in 2014, the company’s new TSV registered dual inline memory module (RDIMM) marks another breakthrough that opens the door for ultra-high capacity memory at the enterprise level. Samsung’s new TSV DRAM module boasts the largest capacity and the highest energy efficiency of any DRAM modules today, while operating at high speed and demonstrating excellent reliability.

“We are pleased that volume production of our high speed, low-power 128GB TSV DRAM module will enable our global IT customers and partners to launch a new generation of enterprise solutions with dramatically improved efficiency and scalability for their investment,” said Joo Sun Choi, executive vice president, Memory Sales and Marketing, Samsung Electronics. “We will continue to expand our technical cooperation with global leaders in servers, consumer electronics and emerging markets, where consumers can benefit from innovative technology that enhances their productivity and the overall user experience.”

The 128GB TSV DDR4 RDIMM is comprised of a total of 144 DDR4 chips, arranged into 36 4GB DRAM packages, each containing four 20-nanometer (nm)-based 8-gigabit (Gb) chips assembled with cutting-edge TSV packaging technology.

Conventional chip packages interconnect die stacks using wire bonding, whereas in TSV packages, the chip dies are ground down to a few dozen micrometers, pierced with hundreds of fine holes and vertically connected by electrodes passing through the holes, allowing for a significant boost in signal transmission. In addition to capitalizing on the industry’s highest capacity and TSV’s advanced circuitry, Samsung’s 128GB TSV DDR4 module has a special design through which the master chip of each 4GB package embeds the data buffer function to optimize module performance and power consumption.

As a result, Samsung’s advanced 128GB TSV DDR4 RDIMM provides a low-power solution for next-generation servers with speeds at up to 2,400 megabits per second (Mbps), achieving nearly twice the performance, while cutting power usage by 50 percent, compared to using the previous highest capacity DRAM modules ─ 64GB LRDIMMs, whose four-chip package stacks are hampered by power and speed limitations caused by their use of conventional wire bonding.

Samsung is responding to growing demand for ultra-high capacity DRAM by accelerating production of TSV technology in the market and quickly ramping up 20nm 8Gb DRAM chips to improve manufacturing productivity. In solidifying its technology leadership and expanding the market for premium memory solutions, the company plans to provide a complete lineup of its new high-performance TSV DRAM modules within the next several weeks including 128GB load reduced DIMMs (LRDIMMs).

In addition, Samsung will continue to maintain its technology leadership by introducing TSV DRAM with higher performance. These will include modules with data transfer speeds of up to 2,667Mbps and 3,200Mbps that help to meet intensifying enterprise server needs, while expanding TSV applications into high bandwidth memory (HBM) and consumer products.

To learn more about TSV, read more here.

Samsung’s Semiconductor Series Part 3

Building state-of-the-art semiconductor chips is one thing but making them into the actual square chips we’re familiar with involves a lot of high-tech, too. This process is called packaging, or back-end manufacturing, where chips are essentially sliced off of the silicon wafer, wired up and encased in epoxy for protection.

Let’s say you have a nice order of milkshake that you want to chug down right now. Organic ingredients with crush-ins of your liking, whatever floats your boat. For that, you would need an efficient apparatus (a.k.a. big enough straw) that can deliver a satisfactory flow of sips, preferably an insulated cup that will keep the frothy integrity of the beverage and temperature-resistant nerves that can hold up to the huge amount of milkshake intake against a massive brain freeze. Similar elements and materials are taken into consideration when chips are packaged. Well, okay, it gets way more complicated with semiconductors, but you get the point.

With the amount of data that need to be processed and the speed that is required today, we want to make sure we offer device manufacturers and consumers the total package, in every sense of the phrase, so that the packaging complements the advanced silicon technology inside. This would also determine the size of the final chip. So yes, packaging solutions, even for semiconductor chips, does matter.

Here are some cool examples of Samsung’s approach to this technology.

Through Silicon Via (TSV) – We talked about increasing cell density on a single chip for higher capacities but another way to achieve that is to stack individual chip dies in a single package. In doing so, the dies are ground from the back as thin as possible, down to several micrometers, so as to minimize the height of the final product.

Instead of the traditional method of connecting the stacked dies externally, we can now pierce hundreds of tiny holes through DRAM dies and then vertically connect them through the holes, allowing faster data processing with less power consumed. This means that if data were in a building, it can just take the elevator downstairs instead of working its way out to the fire escape. Remember, we’re still working in microscopic scales.

TSV allows approximately twice the speed with about half the power compared to packages using the traditional wire bonding. Again, less space, less power consumption and faster data — another reason our DDR4 DRAM using TSV are so awesome.

Read more: Samsung Electronics Starts Mass Production of Industry’s First 8-Gigabit DDR4 Based on 20 Nanometer Process Technology

ePoP – Sleeker mobile devices mean scarcer space for components, so consolidation is very much desired. As such, even chips with different functions can get bundled together and we’ve seen packages come in forms of eMMC (embedded multi-media card: NAND+controller), eMCP (embedded multi-chip package: DRAM+NAND) or PoP (package on package: AP+DRAM). Samsung’s broad chip portfolio encompassing DRAM, NAND and AP, as well as our advanced packaging capabilities in-house, has naturally given us a huge advantage in this department.

Wonder why there aren’t any packages mentioned above incorporating NAND memory and APs? An active AP can get as hot as 80 to 100℃ whereas NAND would normally get ‘fried’ at that temperature. Because of NAND’s low resistance to heat, it’s been considered that it cannot be in the same package as the AP.

Well, guess what — with an out-of-the-box approach and some new techniques, earlier this year, Samsung was able to introduce the industry’s first ePoP (embedded package on package) memory that can be stacked directly on top of an AP.

Our ePoP memory packs a LPDDR3 DRAM and an eMMC together, dramatically shrinking traditional area configurations by about 40 percent. Thanks to its efficiency and small footprint, Samsung’s ePoP memory is now finding itself on board of wearables as well as high-end mobile devices.

Read more: Samsung Electronics Mass Producing High-Density ePoP Memory for Smartphones

Samsung’s Semiconductor Series

Read Part 1. The Itsy-Bitsy Mighty Chip in a Great Big Digital World 

Read Part 2. Physics Busting at Its Seams