February 17, 2016
The DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory internally configured as a eight-bank DRAM. Read and write operation to the DDR2 SDRAM are burst oriented, start at a selected location, and continue for a burst length of four or eight in a programmed sequence. Operation begins with the registration of an Active command, which is then followed by a Read or Write command. Prior to normal operation, the DDR2 SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions and device operation.
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