Samsung Electronics Co., Ltd., the world leader in advanced memory technology, announced that Qualcomm Technologies, Inc. has validated Samsung’s 14-nanometer (nm) based 16-gigabit (Gb) Low Power Double Data Rate 5X (LPDDR5X) DRAM for use on Qualcomm Technologies’ Snapdragon® mobile platforms.

Since developing the industry’s first 14nm-based LPDDR5X DRAM last November, Samsung has worked closely with Qualcomm Technologies to optimize its 7.5 gigabit-per-second (Gbps) LPDDR5X for use with Snapdragon mobile platforms. Delivering about 1.2 times faster speed than the 6.4Gbps LPDDR5 deployed in today’s premium smartphones, Samsung’s LPDDR5X is expected to boost the performance of ultra-high-resolution video recording as well as AI features such as voice recognition, image recognition and natural language processing in next-generation smartphones. Furthermore, by adopting advanced circuit designs as well as dynamic voltage and frequency scaling (DVFS), LPDDR5X power consumption can be reduced by approximately 20%.

“The successful validation of our LPDDR5X solution for Qualcomm Technologies’ Snapdragon mobile platforms is a testament to our leadership in DRAM technology,” said Jinman Han, corporate executive vice president and head of Memory Global Sales & Marketing at Samsung Electronics. “We expect applications for this high-performance, low-power memory to extend beyond smartphones into data center, PC and automotive, enabling more devices and systems to run with greater efficiency.”

“Qualcomm Technologies is an industry leader in enabling and adopting the latest LPDDR DRAM specifications. Enablement of LPDDR5X on Snapdragon platforms will enhance user experiences with new features and improved performance for gaming, camera, and applications using our latest AI Engine across various Qualcomm Technologies’ product lines,” said Ziad Asghar, Vice President of Product Management, Qualcomm Technologies, Inc.

To better accommodate the increasing demand for premium DRAM solutions, Samsung will continually pursue the development of low-power DRAM products that deliver greater performance and even higher capacities in support of a growing array of next-generation systems.

Samsung’s new innovation is considered one of the most challenging packaging technologies for mass production of high-performance chips, as it requires pinpoint accuracy to vertically interconnect 12 DRAM chips through a three-dimensional configuration of more than 60,000 TSV holes, each of which is one-twentieth the thickness of a single strand of human hair.

The thickness of the package (720㎛) remains the same as current 8-layer High Bandwidth Memory-2 (HBM2) products, which is a substantial advancement in component design. This will help customers release next-generation, high-capacity products with higher performance capacity without having to change their system configuration designs.

In addition, the 3D packaging technology also features a shorter data transmission time between chips than the currently existing wire bonding technology, resulting in significantly faster speed and lower power consumption.

“Packaging technology that secures all of the intricacies of ultra-performance memory is becoming tremendously important, with the wide variety of new-age applications, such as artificial intelligence (AI) and High Power Computing (HPC),” said Hong-Joo Baek, executive vice president of TSP (Test & System Package) at Samsung Electronics.

“As Moore’s law scaling reaches its limit, the role of 3D-TSV technology is expected to become even more critical. We want to be at the forefront of this state-of-the-art chip packaging technology.”

Relying on its 12-layer 3D-TSV technology, Samsung will offer the highest DRAM performance for applications that are data-intensive and extremely high-speed.

Also, by increasing the number of stacked layers from eight to 12, Samsung will soon be able to mass produce 24-gigabyte (GB)* High Bandwidth Memory, which provides three times the capacity of 8GB high bandwidth memory on the market today.

Samsung will be able to meet the rapidly growing market demand for high-capacity HBM solutions with its cutting-edge 12-layer 3D TSV technology and it hopes to solidify its leadership in the premium semiconductor market.

*8GB mass-production product= 8Gb x 8 layers, 24GB developed product= 16Gb x 12 layers

*PKG cross section structure

*Wire bonding vs TSV technology