Samsung Electronics, a world leader in advanced semiconductor technology, today unveiled plans for continuous process technology migration to 3- and 2-nanometer (nm) based on the company’s Gate-All-Around (GAA) transistor structure at its 5^th annual Samsung Foundry Forum (SFF) 2021.

With a theme of Adding One More Dimension, the multi-day virtual event is expected to draw over 2,000 global customers and partners. At this year’s event, Samsung will share its vision to bolster its leadership in the rapidly evolving foundry market by taking each respective part of foundry business to the next level: process technology, manufacturing operations and foundry services.

“We will increase our overall production capacity and lead the most advanced technologies while taking silicon scaling a step further and continuing technological innovation by application,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics.” Amid further digitalization prompted by the COVID-19 pandemic, our customers and partners will discover the limitless potential of silicon implementation for delivering the right technology at the right time.”

GAA Is Ready for Customers’ Adoption – 3nm MP in 2022, 2nm in 2025

With its enhanced power, performance and flexible design capability, Samsung’s unique GAA technology, Multi-Bridge-Channel FET (MBCFET^TM), is essential for continuing process migration. Samsung’s first 3nm GAA process node utilizing MBCFET will allow up to 35 percent decrease in area, 30 percent higher performance or 50 percent lower power consumption compared to the 5nm process. In addition to power, performance and area (PPA) improvements, as its process maturity has increased, 3nm’s logic yield is approaching a similar level to the 4nm process, which is currently in mass production.

Samsung is scheduled to start producing its customers’ first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023. Newly added to Samsung’s technology roadmap, the 2nm process node with MBCFET is in the early stages of development with mass production in 2025.

FinFET for CIS, DDI, MCU – 17nm Specialty Process Technology Debuts

Samsung Foundry is continuously improving its FinFET process technology to support specialty products with cost-effective and application-specific competitiveness. A good example of this is the company’s 17nm FinFET process node. In addition to the intrinsic benefits afforded by FinFET, the process node has excellent performance and power efficiency leveraging a 3D transistor architecture. Consequently, Samsung’s 17nm FinFET provides up to 43 percent decrease in area, 39 percent higher performance or a 49 percent increase in power efficiency compared to the 28nm process.

Additionally, Samsung is advancing its 14nm process in order to support 3.3V high voltage or flash-type embedded MRAM (eMRAM) which enables increased write speed and density. It will be a great option for applications such as micro controller units (MCUs), IoT and wearables. Samsung’s 8nm radio frequency (RF) platform is expected to expand the company’s leadership in the 5G semiconductor market from sub-6GHz to mmWave applications.

Looking ahead, in cooperation with its ecosystem partners, Samsung Foundry’s SAFE Forum will be held virtually in November 2021.

A transistor is a semiconductor device used to transform the digital information coded in the binary system into electric signals. A transistor is composed of a ‘channel’ in which the electric current flows between the semiconductor’s source and its drain and a ‘gate’ for managing the electric current traveling through the channel. The gate generates binary system data by amplifying electric signals and also working as a switch. Because of this, the transistor is essentially the basic element of a semiconductor chip.

All digital information, be it in the form documents, photos or videos, is in fact a composed of the binary numeral system, which only uses two symbols, ‘0’ and ‘1’.

In order to increase the number of semiconductor chips mounted on the limited surface of a silicon (Si) substrate, the size of each semiconductor chip naturally needs to be decreased. Furthermore, in order to fit more new and complex functions into each semiconductor chip, the very basic element transistor must become smaller and its power consumption must be minimized to provide the longest possible battery lifespan, as well as reduced heat and electric charges. As electricity consumption is dependent on operating voltage, transistors have been developed so as to decrease operating voltage. Therefore, the history of the semiconductor is synonymous with the history of creating transistors that are smaller, faster and that consume less electricity.

The history of the development of the semiconductor is synonymous with the history of creating transistors that are smaller, faster and that consume less electricity. From the left, Planar Transistor, Fully Depleted (Fin) Transistor, and GAA Transistor

The most widely used transistor in the current semiconductor industry is the Metal-Oxide-Semiconductor (MOS). It consists of a metal electrode, an oxide insulator and a semiconductor channel. The first MOS transistor was of a planar architecture and was structured so that the gate and the channel made contact on one plane. But, as transistors become smaller, the distance between the source and the drain gets smaller, making it difficult for the gates to work as a switch. This is called a ‘short-channel effect’, and along with limiting voltage reduction, it means that planar transistors can only be applied to 20 or above nanometer nodes (or generations)¹.

In order to overcome the short-channel effect, the Fully Depleted transistor emerged as the next generation of transistor. This transistor uses a thin silicon (Si) channel to avoid the short-channel effect by enhancing the ability of the gate to adjust the channel. Its structure format evolved out of that of the conventional transistor (a gate on a plane channel) to become a thin, rugged structure with a standing rectangular channel that interlocks with gates on three sides. As this thin, standing channel somewhat resembles a fish’s dorsal fin, it is also called the ‘fin transistor’. Samsung has been manufacturing fin transistors since 2012 in a range of sizes, starting at just 14 nanometers.

Whereas a planar transistor only allows the channel and the gate to contact in just one plane, a fin transistor has a 3-dimensional structure that allows three sides of a channel (excluding its bottom) to come into contact with the gates. This increased contact with the gates improves semiconductor performance as well as increasing the reduction of operating voltage, solving the problems brought about by the short-channel effect.

Nevertheless, the fin transistor is now facing limitations after several generations of developments and process transitions. Nowadays, the semiconductor industry is increasingly requiring transistors that can reduce operating voltage even further. Despite the fin transistor’s 3-dimensional structure, that only three of the four sides are in contact with gates is now becoming a limitation, as transistors themselves continue to progress and subsequently get smaller.

The evolution of semiconductor transistors

In order to mitigate the limitations of existing transistors solutions, Samsung has developed a new structure, the Gate-All-Around (GAA). As the name suggests, the GAA is a structure that maximizes gates’ channel-controlling function, as all channels, including the fourth bottom one, are covered by gates. The gates provide a 360-degree coverage of the entire channel area to eliminate the short-channel effect, resulting in reducing operating voltage further.

A typical GAA transistor takes the form of a thin and long nanowire². However, a channel needs to be as wide as possible in order to allow a large amount of current to flow through it, and the small diameter of the nanowire makes obtaining this higher current flow difficult. To overcome this, Samsung created and patented their proprietary MBCFET (Multi-Bridge Channel Field Effect Transistor), an optimized version of the GAA transistor. The MBCFET increases the areas that make contact with gates by aligning wire-formed channel structures as a 2-dimensional nanosheets, which enables simpler device integration as well as increasing the electric current. Samsung’s MBCFET is a competitive transistor structure in that it not only includes the means to mitigate the short-channel effect thanks to the GAA structure, but it also increases performance by expanding the channel area.

Compared to existing 7-nanometer fin transistor process technology, the MBCFET decreases power consumption by 50%, improves performance by 30%, and reduces the area that the transistor takes up by 45%.

The development of GAA transistors, tantamount to the Industrial Revolution of semiconductor technology, is such a difficult process that Samsung is the only company currently offering a future delivery plan. Furthermore, the successful creation of the MBCFET is indicative of Samsung’s global industry-leading technological prowess. It has laid the foundation for transforming the semiconductor industry that was set to stall at the 4-nanometer scale, along with providing core technologies necessary for bringing about the fourth industrial revolution.

With this latest market-leading development, Samsung is paving the way for the future of the industry thanks to its collaborative approach and trailblazing technologies.

As a semiconductor engineer working in an industry that is entering an era of transformation brought about by new technology, I am very excited to see what the future holds.

¹Nanometer is a measurement for a semiconductor. 1 nanometer is equal to one billionth of a meter.

²An ultra-tiny line that has one nanometer in section diameter

The event, held today in Santa Clara, California, features top Samsung executives and industry experts reviewing progress on semiconductor technologies and foundry platform solutions that enable developments in artificial intelligence (AI), machine learning, 5G networking, automotive, the Internet of Things (IoT), advanced data centers and many other domains.

“We stand at the verge of the Fourth Industrial Revolution, a new era of high-performance computing and connectivity that will advance the daily lives of everyone on the planet,” said Dr. ES Jung, President and head of Foundry Business at Samsung Electronics.

“Samsung Electronics fully understands that achieving powerful and reliable silicon solutions requires not only the most advanced manufacturing and packaging processes as well as design solutions, but also collaborative foundry-customer relationships grounded on trust and shared vision. This year’s Foundry Forum is filled with compelling evidence of our commitment to progress in all those areas, and we’re honored to host and converse with our industry’s best and brightest,” Dr. Jung added.

Highlights from the U.S. Foundry Forum include:

The New 3nm GAE PDK Version 0.1 is Ready

Samsung’s 3nm Gate-All-Around (GAA) process, 3GAE, development is on track. The company noted today that its Process Design Kit (PDK) version 0.1 for 3GAE has been released in April to help customers get an early start on the design work and enable improved design competitiveness along with reduced turnaround time (TAT).

Compared to 7nm technology, Samsung’s 3GAE process is designed to provide up to a 45 percent reduction in chip area with 50 percent lower power consumption or 35 percent higher performance. The GAA-based process node is expected to be widely adopted in next-generation applications, such as mobile, network, automotive, Artificial Intelligence (AI) and IoT.

Conventional GAA based on nanowire requires a larger number of stacks due to its small effective channel width. On the other hand, Samsung’s patented version of GAA, MBCFET (Multi-Bridge-Channel FET), uses a nanosheet architecture, enabling greater current per stack.

While FinFET structures must modulate the number of fins in a discrete way, MBCFET provides greater design flexibility by controlling the nanosheet width. In addition, MBCFET’s compatibility with FinFET processes means the two can share the same manufacturing technology and equipment, which accelerates process development and production ramp-up.

Samsung recently taped out the 3GAE test vehicle design and will focus on improving its performance and power efficiency going forward.

For more information, please refer to the Newsroom links for GAA infographic and video clip.

The Launching of a New SAFE–Cloud Program

As part of its ongoing efforts to support and enhance customers’ entire design workflow, Samsung Electronics launched the Samsung Advanced Foundry Ecosystem Cloud (SAFE-Cloud) program. It will provide customers with a more flexible design environment through collaboration with major public cloud service providers, such as Amazon Web Services (AWS) and Microsoft Azure, as well as leading Electronic Design Automation (EDA) companies, including Cadence and Synopsys.

To date, most foundry customers have built and managed design infrastructure on their own servers. The SAFE-Cloud program reduces this burden and supports easier, faster and more efficient design efforts by providing an excellent turnkey design environment with extensive process information (PDK, design methodologies), EDA tools, design assets (IP, library) and design services.

Customers can be assured of as much server and storage space as they need, as well as a safe environment optimized for chip design, due to Samsung Electronics’ verification of SAFE-Cloud’s security, applicability and expandability.

Utilizing the SAFE-Cloud platform, Samsung was able to accelerate the development of its 7nm and 5nm cell libraries in collaboration with Synopsys. In addition, Samsung, Gaonchips – a fabless design company in Korea – and Cadence have successfully completed design verification based on the platform.

“Making up-front investments in high-performance computing (HPC) servers and systems can be a challenge for a company like us,” said Kyu Dong Jung, CEO of Gaonchips. “SAFE-Cloud offers us a very flexible design environment without requiring investment in additional infrastructure, as well as reduced design TAT. I expect this program to provide more tangible business and technical benefits to us and the entire fabless industry.”

Process Technology Roadmap and Advanced Packaging Updates  

Samsung’s roadmap includes four FinFET-based processes from 7nm down to 4nm that leverage extreme ultraviolet (EUV) technology as well as 3nm GAA, or MBCFET.

In the second half of this year, Samsung is scheduled to start the mass production of 6nm process devices and complete the development of 4nm process.

The product design of Samsung’s 5nm FinFET process, which was developed in April, is expected to be completed in the second half of this year and go under mass production in the first half of 2020.

Extensions of the company’s FD-SOI (FDS) process and eMRAM together with an expanded set of state-of-the-art package solutions were also unveiled at this year’s Foundry Forum. Development of the successor to the 28FDS process, 18FDS, and eMRAM with 1Gb capacity will be finished this year.

In order to reduce the size of semiconductors, FinFET architecture was introduced to further scale gate length. As Samsung designed even smaller microchips, new challenges arose, and achieving below 4-5 nm has proved difficult when using the current FinFET transistor architecture. This observation has spurred the company to innovate and implement its new Gate-All-Around (GAA) transistors.

Samsung re-designed the existing GAA to become the Multi Bridge Channel FET (MBCFET). The MBCFET is more power-efficient than the GAA, and its performance is subsequently better. Samsung’s patented MBCFET is formed as a nanosheet, allowing for a larger current and simpler device integration.

Take a look at the infographic below to learn more about how Samsung’s GAA is advancing the future of semiconductor technology.