Young Hyun Jun, Vice Chairman and Head of Device Solutions (DS) Division, was named CEO and will also become the Head of Memory Business and Samsung Advanced Institute of Technology. Jinman Han was promoted to President and will become the Head of Foundry Business, while Seok Woo Nam will become Chief Technology Officer of Foundry Business, a newly-created position.

JH Han, Vice Chairman, CEO and Head of Device eXperience (DX) Division, will also lead a newly-created committee that will focus on strengthening product quality across the company.

Jinman Han was previously Executive Vice President and President of Device Solutions America, leading the Company’s semiconductor business in the U.S. Previously, he worked in design teams for DRAM and Flash memory and has also led SSD development and strategic marketing.

Seok Woo Nam, previously President and Head of FAB Engineering & Operations, is an expert in semiconductor process development and manufacturing with extensive experience in memory process technology and foundry manufacturing technology.

Hansung Ko, CEO of Samsung Bioepis, has vast experience in developing new business areas such as biotechnology and is expected to lead efforts in finding new growth opportunities.

Other changes in today’s announcement include:

• Yong Kwan Kim, named President of Management Strategy at DS Division; previously Executive Vice President of Business Support TF

• Wonjin Lee, named President and Head of Global Marketing Office; previously executive advisor for Samsung Electronics

• President Hark Kyu Park will move to the Business Support TF; previously Chief Financial Officer

Samsung Electronics today announced it has been recognized by Interbrand, a global brand consultancy, as a “Global Top 5” brand for the fifth year in a row. Interbrand releases its list of “Best Global Brands” each year, and on this year’s list, it was revealed that Samsung’s brand value reached $100.8 billion and grew by 10% year-on-year.

The significant increase of Samsung Electronics’ brand value was driven by growth in the AI industry, particularly its leadership in on-device AI and competitiveness in the semiconductor sector. Since its first top five ranking in 2020, Samsung Electronics has experienced an impressive 62% growth over four years and remains the only Asian business among the global top five brands.

“This year’s substantial brand growth is a direct result of our holistic approach to AI and efforts to put this powerful technology into the hands of Samsung users around the world,” said YH Lee, President and Head of the Global Marketing Office at Samsung Electronics. “Moving forward, we will lean even further into the qualities that our users have come to both love and expect.”

Company Recognized for On-Device AI, enhanced connected experiences and AI Leadership

According to Interbrand, Samsung Electronics’ evaluation was positively influenced by the following:

• Deployment of AI technologies in key products and leadership in the on-device AI market
• Enhanced connected experiences through AI-enabled platforms and products
• AI leadership based on its competitiveness in the semiconductor sector
• Implementing a consistent brand strategy in the global market
• Ongoing commitment to a more sustainable future.

This year, under the vision of AI for All, Samsung is expanding its portfolio of products infused with AI technologies to enhance customer experiences. With the release of the Galaxy S24 series, Samsung has been leading the mobile AI. It has also launched AI TVs equipped with AI processors and AI upscaling while introducing Bespoke AI appliances that empower user’s daily life.

The company is expanding the SmartThings ecosystem to provide a unified connectivity experience, enabling not just its own products, but also various third-party devices. This integration offers substantial benefits that go beyond more convenience, including energy conservation and family care.

As a leader in the semiconductor industry, Samsung is making bold investments in R&D to meet rising AI demand and — with innovative memory products like DDR5, GDDR7, HBM3E, LPDDR5X, 9^th Gen V-NAND, Exynos SoC, high resolution image sensor— is proactively addressing server and on-device AI needs.

As for brand strategy, the company has been recognized for delivering consistent brand values and build authentic relationships with customers.

Additionally, Samsung focuses on implementing environmentally conscious activities and initiatives by adopting various recycled materials across a wide range of product categories. It has participated in global initiatives and collaborated with industry leaders with focus on goals such as reducing carbon emissions associated with device usage. Samsung Electronics’ sustainability efforts as well as fostering a diverse corporate culture have also received positive evaluations.

Samsung’s Recognized Efforts in Each Business Division

Mobile

• Leading the mobile AI era with Galaxy AI following the release of the Galaxy S24 series
• Making the new Galaxy AI upleveled by the unique Galaxy Z Fold6 and Z Flip6 foldable experience
• Strengthening leadership in the health AI with the release of the Galaxy Ring and new Galaxy Watch series

Networks

• Strengthening leadership in virtualized Radio Access Network (vRAN) and Open RAN
• Leading the technical standardization of 6G
• Consistently innovating technologies to support various 5G use cases, including streaming and gaming
• Enhancing partnerships with customer companies and communicating the sustainability aspects of Samsung’s network technology

Visual Display

• Solidifying global leadership in the TV and soundbar markets
• Consistently innovating with products like AI TVs, MICRO LED displays and the Music Frame
• Innovating the viewing experience with cutting-edge technologies, including AI upscaling and Active Voice Amplifier Pro
• Positioning itself as a core gaming partner through various partnerships
• Strengthening security and privacy through Samsung Knox

Digital Appliances

• Maintaining global leadership in categories such as refrigerators and washing machines through consistent product innovation and advanced AI capabilities
• Providing customer-centered value and experience through Bespoke AI appliances
• Enhancing accessibility with Auto Open Door and the upgraded Bixby voice control
• Offering substantial benefits — such as energy efficiency through SmartThings AI Energy Mode — and the expansion of SmartThings connectivity experience worldwide

Semiconductor

• Delivering the industry’s first GDDR7 DRAM, HBM3E DRAM, LPDDR5X DRAM and 9^th Gen V-NAND as well as solidifying market leadership for the AI era
• Consistently advancing AI technologies such as ISOCELL Auto 1H1 sensors, optimized for the development of autonomous vehicles
• Exceeding customer expectations with the consistent rollout of exceptional B2C SSD products like 990 EVO and SSD T9

Interbrand’s Best Global Brands are listed according to the evaluation of each brand value, which is a result of comprehensive analysis of the financial performance of the company, the influence of the brand on customer purchases and brand competitiveness (strategy, empathy, differentiation, customer engagement, consistency, trust, etc.). It is a brand value evaluation with one of the longest histories in the world and is widely recognized for its credibility.

Samsung Electronics, a world leader in advanced semiconductor technology, today unveiled its latest foundry innovations and outlined its vision for the AI era during Samsung Foundry Forum (SFF) U.S., an annual event held at the company’s Device Solutions America headquarters in San Jose, California.

Under the theme “Empowering the AI Revolution,” Samsung announced its reinforced process technology roadmap, including two new cutting-edge nodes — SF2Z and SF4U — as well as its integrated Samsung AI Solutions platform harnessing the unique strengths of its Foundry, Memory and Advanced Package (AVP) businesses.

“At a time when numerous technologies are evolving around AI, the key to its implementation lies in high-performance, low-power semiconductors,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. “Alongside our proven GAA process optimized for AI chips, we plan to introduce integrated, co-packaged optics (CPO) technology for high-speed, low-power data processing, providing our customers with the one-stop AI solutions they need to thrive in this transformative era.”

The event featured presentations from distinguished industry thought leaders such as Arm CEO Rene Haas and Groq CEO Jonathan Ross, who took the stage to emphasize the robust partnerships with Samsung in tackling new AI challenges. Around 30 partner companies exhibited at booths, further highlighting the dynamic collaboration across the U.S. foundry ecosystem.

Empowering Customer AI Solutions With State-of-the-Art Process Technology Roadmap

Samsung announced two new process nodes, SF2Z and SF4U, reinforcing its leading-edge process technology roadmap.

The company’s latest 2nm process, SF2Z, incorporates optimized backside power delivery network (BSPDN) technology, which places power rails on the backside of the wafer to eliminate bottlenecks between the power and signal lines. Applying BSPDN technology to SF2Z not only enhances power, performance and area (PPA) compared to SF2, the first-generation 2nm node, but also significantly reduces voltage drop (IR drop), enhancing the performance of HPC designs. Mass production of SF2Z is slated for 2027.

SF4U, on the other hand, is a high-value 4nm variant that offers PPA improvements by incorporating optical shrink, with mass production scheduled for 2025.

Samsung reaffirmed that its preparations for SF1.4 (1.4nm) are progressing smoothly, with performance and yield targets on track for mass production in 2027. Emphasizing its ongoing commitment to advancing beyond Moore, Samsung is actively shaping future process technologies below 1.4nm through material and structural innovations.

Continuously Advancing GAA Maturity

With the onset of the AI era, structural advancements like gate-all-around (GAA) have become imperative to meet power and performance demands. At SFF, Samsung emphasized the maturity of its GAA technology, a key technological enabler in empowering AI.

Entering its third year of mass production, Samsung’s GAA process is consistently demonstrating continuous maturity in both yield and performance. Leveraging this accumulated GAA production experience, Samsung plans to mass produce its second-generation 3nm process (SF3) in the second half of this year and deliver GAA on its upcoming 2nm process.

Samsung’s GAA production has been steadily increasing since 2022 and is poised to substantially expand in the coming years.

Highlighting Cross-Company Collaborations for Turnkey Samsung AI Solutions

Another highlight was the unveiling of Samsung AI Solutions, a turnkey AI platform resulting from collaborative efforts across the company’s Foundry, Memory and AVP businesses.

Integrating the unique strengths of each business, Samsung is offering high-performance, low-power and high-bandwidth solutions that can be tailored to suit specific customer AI requirements.

Cross-company collaboration also streamlines supply chain management (SCM) and reduces time to market, enabling a remarkable 20% improvement in total turnaround time (TAT).

Samsung plans to introduce an all-in-one, CPO-integrated AI solution in 2027, aiming to provide customers with one-stop AI solutions.

Diversifying Customers and Applications for a Balanced Portfolio Across AI to Mainstream Tech

Samsung is also making significant strides in diversifying its customer base and application areas.

Over the past year, close customer collaborations have led to an increase in Samsung Foundry’s AI sales by 80%, reflecting its dedication to meeting evolving market demands.

In addition to its leading-edge process nodes, Samsung offers specialty and 8-inch wafer derivatives with continued PPA improvements and strong cost competitiveness. With this balanced technology portfolio, the company is catering to customer needs across automotive, medical, wearable and IoT applications.

Converging AI and Technology to Advance the Foundry Ecosystem Toward Collective Growth

Building on the momentum of the SFF event, Samsung will also be hosting its annual Samsung Advanced Foundry Ecosystem (SAFE) Forum on June 13. Themed “AI: Exploring Possibilities and Future,” the forum will serve as a collaborative platform for ecosystem partners to discuss customizable technologies and solutions tailored for AI.

At this year’s forum, Siemens CEO Mike Ellow, AMD Vice President Bill En and Celestial AI CEO David Lazovsky are among the industry leaders who will present insightful perspectives on the future of chip and system design technologies.

The forum will also feature the inaugural Multi-Die Integration (MDI) Alliance workshop, following the launch of the MDI Alliance last year. Samsung will engage in extensive discussions with its alliance partners on mutual growth opportunities and specific collaborative initiatives, with a focus on 2.5D and 3D IC designs for comprehensive solutions development. These activities will further strengthen partnerships and foster a collective vision.

Samsung Electronics, a world leader in advanced semiconductor technology, today hosted Samsung Foundry Forum (SFF) 2023 Europe and unveiled its advanced and wide ranging automotive process solutions, from the most advanced 2-nanometer process to the 8-inch legacy process.

Alongside its customers and Samsung Advanced Foundry Ecosystem (SAFE) partners, Samsung Electronics showcased the latest technological trends and its business strategy tailored to the European market.

“Samsung Foundry is driving innovation in next-generation solutions to build an expanded portfolio that meets the growing needs of our automotive customers, especially as the era of electric vehicles becomes a reality,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. “We are strengthening our readiness to provide customers with distinguished service across a variety of solutions, including power semiconductors, microcontrollers and advanced AI chips for autonomous driving.”

Since participating in IAA Mobility 2023 for the first time in September, Samsung Electronics is strengthening engagement and partnership in specialty processes for automotive customers in the European market, further solidifying its status as a leading foundry partner for the industry.

Pioneering New Applications With Industry’s Most Advanced eMRAM

In order to meet the needs of the latest advancements in the automotive market, Samsung is setting out to develop the industry’s first 5-nanometer eMRAM for next-generation automotive technology. eMRAM is a next-generation memory semiconductor used for automotive applications that enables high read and write speeds as well as superior heat resistance.

Since developing and mass producing the industry’s first 28nm FD-SOI¹ based eMRAM in 2019, Samsung Electronics has been developing 14nm for the FinFET process based on AEC-Q100 Grade 1. Samsung Foundry plans to expand its eMRAM portfolio by adding 14nm by 2024, 8nm by 2026, and 5nm by 2027.

Samsung’s 8nm eMRAM shows potential to deliver a 30% increase in density and 33% increase in speed, compared to the 14nm process.

Tackling the Market With Automotive Process Solutions From Cutting-Edge to Legacy

The company announced its advanced process roadmap, highlighting its plans to complete mass production readiness for its 2nm process for automotive applications by 2026.

Samsung Electronics is also bolstering its readiness to serve customer needs by expanding its 8-inch BCD (Bipolar-CMOS-DMOS) process portfolio. The BCD process combines the strengths of three different process technologies: Bipolar (B), CMOS (C), and DMOS (D) on one chip and is most commonly used in the production of power semiconductors.

Samsung Electronics plans to expand its current 130nm automotive BCD process to add 90nm by 2025. The 90nm BCD process is expected to bring a 20% decrease in chip area compared to the 130nm process.

Implementing Deep Trench Isolation (DTI) technology, which reduces the distance between each transistor to maximize the performance of power semiconductors, Samsung Foundry will be able to apply a greater voltage of 120V instead of 70V to a wider range of applications. This will enable readiness to provide a process development kit (PDK) that implements 120V to the 130nm BCD process by 2025.

Leading ‘Beyond-Moore’ Innovation Through Advanced Packaging Alliance

Samsung established a Multi-Die Integration (MDI) Alliance by collaborating with its SAFE partners as well as major players in memory, package substrate, and testing.

As part of an industry-wide partnership with 20 partners, Samsung is leading the development of 2.5D and 3D packaging solutions customized for all applications from automotive to high-performance computing (HPC).

Samsung Electronics hosted the annual Samsung Foundry Forum 2023 in the United States on June 27-28, in South Korea on July 4, and in Japan on October 17. The content from the forum will be available on the Samsung Semiconductor website for worldwide access to all visitors beginning November 2.

¹ Fully Depleted Silicon On Insulator (FD-SOI) is a planar process technology that implements an impervious insulating film (SiO2) on top of a silicon wafer and builds transistors on top of it to minimize leakage.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced its latest foundry technology innovations and business strategy at the 7^th annual Samsung Foundry Forum (SFF) 2023.

Under the theme “Innovation Beyond Boundaries,” this year’s forum delved into Samsung Foundry’s mission to address customer needs in the artificial intelligence (AI) era through advanced semiconductor technology.

Over 700 guests, from customers and partners of Samsung Foundry, attended this year’s event, of which 38 companies hosted their own booths to share the latest technology trends in the foundry industry.

“Samsung Foundry has always met customer needs by being ahead of the technology innovation curve, and today, we are confident that our gate-all-around (GAA)-based advanced node technology will be instrumental in supporting the needs of our customers using AI applications,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. “Ensuring the success of our customers is the most central value to our foundry services.”

As part of its business strategy to solidify its competitiveness as a leading foundry service, Samsung Foundry today announced the following:

• Expanded applications of its 2-nanometer (nm) process and specialty process
• Expanded production capacity at its Pyeongtaek fab Line 3 (P3)
• Launched a new “Multi-Die Integration (MDI) Alliance” for next-generation packaging technology
• Continued progress in the foundry ecosystem with Samsung Advanced Foundry Ecosystem (SAFE) partners

Leading the Industry With Expanded 2nm Applications and Specialty Processes

At the event, Samsung announced detailed plans for the mass production of its 2nm process, as well as performance levels.

The company will begin mass production of the 2nm process for mobile applications in 2025, then expand to HPC in 2026 and automotive in 2027. Samsung’s 2nm process (SF2) has shown a 12% increase in performance, a 25% increase in power efficiency and a 5% decrease in area, when compared to its 3nm process (SF3).

Mass production of SF1.4 will begin in 2027 as planned.

From 2025, Samsung will begin foundry services for 8-inch gallium nitride (GaN) power semiconductors targeting consumer, data center and automotive applications.

To secure the most cutting-edge technology in 6G, the 5nm Radio Frequency (RF) is also under development and will be available in the first half of 2025. Samsung’s 5nm RF process shows a 40% increase in power efficiency and a 50% decrease in area compared to the previous 14nm process.

In addition, the company will add automotive applications to its 8nm and 14nm RF, expanding beyond the mobile applications currently under mass production.

Stabilizing the Supply Chain and Meeting Customer Needs With Expanded Capacity

Under the “Shell-First” operation strategy that aims to better respond to customer demands, Samsung Foundry is maintaining its commitment to invest and build capacity by adding new manufacturing lines in Pyeongtaek, South Korea, and Taylor, Texas. Current expansion plans will increase the company’s clean room capacity by 7.3 times by 2027 compared to 2021.

The company plans to begin mass production of foundry products for mobile and other applications at Pyeongtaek Line 3 in the second half of the year. Samsung is also focusing on increasing its manufacturing capacity in the United States. Construction of the new fab in Taylor is proceeding according to initial plans and is expected to finish by the end of the year, beginning operation in the second half of 2024.

Samsung will continue to expand its production base to Yongin, South Korea, to power the next generation of Samsung’s foundry services. Yongin is a nearby city located about 10km east of Samsung’s Hwaseong and Giheung campuses.

Leading the “Beyond Moore” Era With New Multi-Die Integration Alliance

In a bid to address the rapid growth in the chiplet market for mobile and HPC applications, Samsung is launching the MDI Alliance in collaboration with its partner companies as well as major players in memory, substrate packaging and testing.

The MDI Alliance leads innovation in stacking technology by forming a packaging technology ecosystem for 2.5D and 3D Heterogeneous Integration. Together with partners across the ecosystem, Samsung will provide a one-stop turnkey service to better support customers’ technological innovation.

Samsung plans to actively respond to customer and market needs by developing customized packaging solutions that are tailored to the individual needs of various applications including HPC and automotive.

Pushing Boundaries With Partners for Enhanced Fabless Support

Following the Samsung Foundry Forum, Samsung will be hosting the Samsung Advanced Foundry Ecosystem (SAFE) Forum on June 28 under the theme “Accelerating the Speed of Innovation.”

Together with over a hundred partners across electronic design automation (EDA), design solution partners (DSP), outsourced semiconductor assembly and test (OSAT), cloud and IP, Samsung is promoting mutual growth of the foundry ecosystem to power the success of customers.

Samsung has long supported stronger collaboration between partners across the foundry ecosystem, advancing the boundaries of design infrastructure from 8-inch to the latest GAA process. Samsung and its 23 EDA partners now offer over 80 design tools and is also collaborating with 10 OSAT partners to develop 2.5D/3D packaging design solutions.

Samsung provides product design services to a variety of customers from startups to industry leaders through strong partnerships with nine DSP partners that have extensive expertise in Samsung Foundry processes, as well as nine Cloud partners.

Samsung has also secured a portfolio of over 4,500 key IPs from 50 global IP partners. Samsung plans to secure additional next-generation high-speed interface IPs for SF2, including LPDDR5x, HBM3P, PCIe Gen6 and 112G SerDes. Its long-term partnerships with leading global IP providers in their respective fields will help cater to customer needs in AI, HPC and automotive.

“Through extensive collaboration with our SAFE partners, Samsung Foundry is helping simplify designs that are becoming even more complex amid the application of the most advanced processes and new technologies such as heterogeneous integration,” said Jong-wook Kye, Executive Vice President and Head of Design Platform Development, Foundry Business at Samsung Electronics. “We will continue to strive for consistent growth in the Samsung Foundry ecosystem in terms of both scale and quality.”

Samsung Electronics will be hosting the Samsung Foundry Forum 2023 in South Korea in July, and the event will expand to Europe and Asia later in the year to meet customers in each region.

▲ Integrated Ambarella CV3-AD685 system-on-chip built on Samsung Foundry’s 5nm technology

Samsung Electronics, a world leader in advanced semiconductor technology, and Ambarella, Inc. (NASDAQ: AMBA), an edge AI semiconductor company, today announced that Samsung’s Foundry business is providing its 5-nanometer (nm) process technology to Ambarella for its newly announced CV3-AD685 automotive AI central domain controller. This collaboration will help transform the next generation of autonomous driving vehicle safety systems by bringing new levels of AI processing performance, power and reliability.

The CV3-AD685 is the first production version of Ambarella’s CV3-AD family of automotive AI central domain controllers with Tier-1 automotive suppliers announcing they will offer solutions using the CV3-AD system-on-chip (SoC) product family. Samsung’s 5nm process technology is optimized for automotive-grade semiconductors with extremely tight process controls and advanced IP for exceptional reliability and outstanding traceability.

Ambarella will rely on Samsung’s 5nm process maturity and the technology’s solid track record. This 5nm process is backed by the company’s extensive experience in automotive foundry process, IP and service package development to enable manufacturers to create cutting-edge innovations in assisted and automated mobility.

“Ambarella and Samsung Foundry have a rich history of collaboration, and we are excited to bring their world-class 5nm technology to our new CV3-AD685 SoCs,” said Fermi Wang, President and CEO at Ambarella. “Samsung’s proven automotive process technology allows us to bring new levels of AI acceleration, systems integration and power efficiency to ADAS and L2+ through L4 autonomous vehicles.”

The CV3-AD685 integrates Ambarella’s next-generation CVflow^® AI engine, which includes neural network processing that is 20 times faster than the previous generation of Ambarella’s CV2 SoCs. It also provides general-vector and neural-vector processing capabilities to deliver the overall performance required for full autonomous driving (AD) stack processing, including computer vision, 4D imaging radar, deep sensor fusion and path planning.

“Samsung brings 5nm EUV FinFET technology to automotive applications for unprecedented ADAS and vision processor performance,” said Sang-Pil Sim, Executive Vice President and Head of Foundry Corporate Planning at Samsung Electronics. “With Tier-1 automotive suppliers already adopting the technology, we believe other automotive companies will also consider using the Ambarella CV3-AD SoC product family manufactured in Samsung’s 5nm process.”

The CV3-AD685 will be the first in the CV3-AD product family to use Samsung’s 5nm process, and this SoC integrates advanced image processing, a dense stereo and optical flow engine, ARM^® Cortex^® A78AE and R52 CPUs, an automotive GPU for visualizations, and a hardware security module (HSM). It features an “algorithm first” architecture that provides support for the entire autonomous-driving software stack.

The high-performance, power efficient and scalable CV3-AD family, which is built specifically for ADAS, complements a wide range of solutions for assisted driving while advancing vehicle automation. The integrated CV3-AD685 SoC enables information from various sensors to be fused for robust L2+ to L4 autonomous driving. Samsung Foundry’s industry-leading process technology and advanced 3D-packaging solutions are powering many of the latest mobile, HPC and automotive solutions.

Samsung’s 5nm process is also backed by the Samsung Advanced Foundry Ecosystem (SAFE) program. The SAFE program ensures close collaboration between Samsung Foundry, ecosystem partners and customers to deliver robust SoC designs based on certified key design components including Process Design Kits (PDK), reference flows with Design Methodologies (DM), a variety of Intellectual Properties (IP), and on-demand design support.

About Ambarella

Ambarella’s products are used in a wide variety of human vision and edge AI applications, including video security, advanced driver assistance systems (ADAS), electronic mirror, drive recorder, driver/cabin monitoring, autonomous driving and robotics applications. Ambarella’s low-power systems-on-chip (SoCs) offer high-resolution video compression, advanced image and radar processing and powerful deep neural network processing to enable intelligent perception, fusion and planning. For more information, please visit www.ambarella.com.

With significant market growth in high-performance computing (HPC), artificial intelligence (AI), 5/6G connectivity and automotive applications, demand for advanced semiconductors has increased dramatically, making innovation in semiconductor process technology critical to the business success of foundry customers. To that end, Samsung highlighted its commitment to bringing its most advanced process technology, 1.4-nanometer (nm), for mass production in 2027.

During the event, Samsung also outlined steps its Foundry Business is taking in order to meet customers’ needs, including: △foundry process technology innovation, △process technology optimization for each specific applications, △stable production capabilities and △customized services for customers.

▲ Dr. Siyoung Choi, president and head of Foundry Business at Samsung Electronics, is giving his keynote speech at Samsung Foundry Forum 2022.

“The technology development goal down to 1.4nm and foundry platforms specialized for each application, together with stable supply through consistent investment are all part of Samsung’s strategies to secure customers’ trust and support their success,” said Dr. Siyoung Choi, president and head of Foundry Business at Samsung Electronics. “Realizing every customer’s innovations with our partners has been at the core of our foundry service.”

Showcasing Samsung’s Advanced Node Roadmap Down to 1.4nm in 2027

With the company’s success of bringing the latest 3nm process technology to mass production, Samsung will be further enhancing gate-all-around (GAA) based technology and plans to introduce the 2nm process in 2025 and 1.4nm process in 2027.

While pioneering process technologies, Samsung is also accelerating the development of 2.5D/3D heterogeneous integration packaging technology to provide a total system solution in foundry services.

Through continuous innovation, its 3D packaging X-Cube with micro-bump interconnection will be ready for mass production in 2024, and bump-less X-Cube will be available in 2026.

▲ Dr. Siyoung Choi, president and head of Foundry Business at Samsung Electronics, is giving his keynote speech at Samsung Foundry Forum 2022.

Proportion of HPC, Automotive and 5G To Be More Than 50% by 2027

Samsung actively plans to target high-performance and low-power semiconductor markets such as HPC, automotive, 5G and the Internet of Things (IoT).

To better meet customers’ needs, customized and tailored process nodes were introduced during this year’s Foundry Forum. Samsung will enhance its GAA-based 3nm process support for HPC and mobile, while further diversifying the 4nm process specialized for HPC and automotive applications.

For automotive customers specifically, Samsung is currently providing embedded non-volatile memory (eNVM) solutions based on 28nm technology. In order to support automotive-grade reliability, the company plans to further expand process nodes by launching 14nm eNVM solutions in 2024 and adding 8nm eNVM in the future. Samsung has been mass producing 8nm RF following 14nm RF, and 5nm RF is currently in development.

‘Shell-First’ Operation Strategy To Respond to Customer Needs in a Timely Manner

Samsung plans to expand its production capacity for the advanced nodes by more than three times by 2027 compared to this year.

Including the new fab under construction in Taylor, Texas, Samsung’s foundry manufacturing lines are currently in five locations: Giheung, Hwaseong and Pyeongtaek in Korea; and Austin and Taylor in the United States.

At the event, Samsung detailed its ‘Shell-First’ strategy for capacity investment, building cleanrooms first irrespective of market conditions. With cleanrooms readily available, fab equipment can be installed later and set up flexibly as needed in line with future demand. Through the new investment strategy, Samsung will be able to better respond to customers’ demands.

Investment plans in a new ‘Shell-First’ manufacturing line in Taylor, following the first line announced last year, as well as potential expansion of Samsung’s global semiconductor production network were also introduced.

Expanding the SAFE Ecosystem To Strengthen Customized Services

Following the ‘Samsung Foundry Forum,’ Samsung will hold the ‘SAFE Forum’ (Samsung Advanced Foundry Ecosystem) on October 4th. New foundry technologies and strategies with ecosystem partners will be introduced encompassing areas such as Electronic Design Automation (EDA), IP, Outsourced Semiconductor Assembly and Test (OSAT), Design Solution Partner (DSP) and the Cloud.

In addition to 70 partner presentations, Samsung Design Platform team leaders will introduce the possibility of applying Samsung’s processes such as Design Technology Co-Optimization for GAA and 2.5D/3DIC.

As of 2022, Samsung provides more than 4,000 IPs with 56 partners, and is also cooperating with nine and 22 partners in the design solution and EDA, respectively. It also offers cloud services with nine partners and packaging services with 10 partners.

Along with its ecosystem partners, Samsung provides integrated services that support solutions from IC design to 2.5D/3D packages.

Through its robust SAFE ecosystem, Samsung plans to identify new fabless customers by strengthening customized services with improved performance, rapid delivery and price competitiveness, while actively attracting new customers such as hyperscalers and start-ups.

Starting in the United States (San Jose) on October 3rd, the ‘Samsung Foundry Forum’ will be sequentially held in Europe (Munich, Germany) on the 7th, Japan (Tokyo) on the 18th and Korea (Seoul) on the 20th, through which customized solutions for each region will be introduced. A recording of the event will be available online from the 21st for those who were unable to attend in person.

Supporting Fast, Smooth Telecommunication Anywhere: The Ultra-High Performing Modem with AI Technology

The term “modem” encompasses all types, from the dial-up modems used in the 1990s to connect PCs to the Internet, to wired communication modems like digital subscriber line (DSL) and cable, to wireless communication modems for cellular service and Wi-Fi. However, when we talk about modems today in the mobile industry, the term usually refers to cellular modems for wireless communication that support LTE and 5G.

In a smartphone, the terminal modem is in charge of making calls and transmitting and receiving data by exchanging signals with base stations. The reason we can make calls and seamlessly watch videos anywhere is all thanks to high-performing cellular modems. Today, the latest cellular modems support technologies from 2G to 5G. 

Cellular modems were first used for 1G when only phone calls could be made using the analog communication method. In the 2G era, the digital communication method¹ was introduced, and additional services such as the short message service (SMS) became possible. 3G enabled the use of the Internet on mobile phones, laying the foundation for mobile broadband,² and 4G ushered in the true mobile broadband era that made seamlessly watching HD videos possible. The speed of 5G, which Korea was first in the world to commercialize in 2019, now reaches the 10Gbps level, and various applications other than mobile devices are being created using this low-latency and hyper-connectivity technology. 

▲ A comparison of the characteristics of different mobile communication generations.

With the advent of the LTE era, data transmission speeds have become remarkably higher, and mobile phones can now provide functions almost identical to those provided by computers. Having experimented with developing its own modem before the 2000s, Samsung Electronics began developing an LTE modem chip in earnest in 2007 and became the first in the world to succeed in LTE modem commercialization in 2009, after mastering 2G and 3G technologies.

▲ The communication process between a modem and a base station.

In 2012, the Galaxy S series was equipped with Samsung’s LTE modems for the first time. In 2019, the 5G-integrated SoC Exynos, the first ever chip to combine a 5G communication modem and a mobile AP, was developed. Exynos improved energy efficiency by combining two chips with different functions into one as well as the ease of design for smartphone manufacturers by reducing the area taken up by the component. Currently, Exynos’ 5G³ modem supports not only the sub-6GHz band but also extremely high frequency bands (i.e., mmWave), such as 28GHz and 39GHz. Thanks to this, sub-6GHz increases service coverage, and ultra-high-speed communication is offered with mmWave near base stations. 

Today, Samsung is one of the world’s top three 5G modem design companies. “Generally, the process for developing a modem is complicated because it must support new technology like 5G and already commercialized technologies like 3G and LTE. As it also requires a significant investment, there are only a handful of modem chip companies in the world,” said Vice President Jungwon Lee, a signal processing expert who currently leads the Modem Development Team in the System LSI Business after working at Samsung DS America and at Samsung Research America. “It is an area that also requires a lot of development time, from algorithm development to chip design, software development and field testing.”

▲ Vice President Jungwon Lee (right) and PL Huiwon Je (left) of the Modem Development Team strive to improve the development performance of cellular modems.

Samsung is conducting field tests in countries around the world to improve service coverage as much as possible and making various efforts to improve the baseband signal processing method, including the use of artificial intelligence (AI) technology to increase transmission speeds. As a result, the company successfully created a modem that utilizes AI algorithms last year, although it is yet to be commercialized. “Modems with AI technology can promote performance enhancements by minimizing the processing of interference signals or increasing energy efficiency through the use of AI processors,” said Lee.

In addition to 5G, Samsung is currently actively working on the development of 6G technology. “Right now, we are focused on developing the world’s best 5G modem and 5G-Advanced modem, and we are preparing for 6G modem technology research in collaboration with Samsung DS America and Samsung Research for the imminent 6G era,” said Lee. His achievements in modem signal processing technology were recognized when he was selected as a Fellow of the IEEE.⁴

“6G modems are expected to enable 1Tbps-level speeds, support various communication networks including satellite communication, and be widely used in various applications, such as automobiles, IoT and AR/VR — going far beyond smartphones,” he said. “To pave the way for the 6G era, we must have the backing and support of various frequency bands, including the terahertz (THz) band, multi-antenna support for at least hundreds of antennas, advanced AI technology and communication network signal efficiency technology.”

Meanwhile, Lee is leading the way for Samsung as the company aims to create the best modem for Android. “We are expanding our 5G business in the short run while striving to secure a leading position early on in the 6G era in the medium to long-term,” he said. Samsung plans to drastically increase the headcount of the Modem Development Team to improve such performance and to expand related business markets. 

“I am proud to be a part of the development team of a major global company that leads modem technology. On a more personal note, I find it fascinating to see how what I learned from theories can actually be implemented in many cases when applied to products,” said Lee when asked why he was so drawn to modems. “Today, having seamless telephone conversations anytime and anywhere and the high-speed internet experience have become a fundamental part of life. The thing that has allowed us to experience this convenient life is modems, and the Modem Development Team is enthusiastic about continuing to play its role in these developments.”

Making an Extensive Connectivity Environment That Works Quickly and Fluidly

The two main telecommunication standards for mobile wireless communications are cellular networks and connectivity. The cellular network represented by the 3GPP standard⁵ refers to telecommunication standards such as CDMA, LTE and 5G. It provides a wide range of service coverages in certain bandwidths licensed for mobile carriers and does this via the infrastructure of various base stations. Connectivity, on the other hand, is represented by IEEE 802.11(Wi-Fi)/802.15 (Bluetooth, ZigBee, UWB⁶). It utilizes Industry-Science-Medical (ISM) bandwidth that can be used by anyone. Connectivity follows local telecommunication standards for indoors and provides service to all.

▲ The types of Wi-Fi protocols for wireless connection

“Cellular network” is a service with an infrastructure based on mobility and is mainly operated by establishing networks that cover wide areas. On the other hand, “connectivity” provides wireless access among devices within a short distance without using infra-networks established by operators. This allows for the convenience of portability without wires. In particular, Wi-Fi boasts a faster transmission speed more reliably than cellular networks over relatively long distances, especially indoors. This is why Wi-Fi is so widely used for connecting mobile phones, laptops and so on. Just like peer-to-peer (P2P), Wi-Fi is better for selective and intensive telecommunication that can, when necessary, facilitate high transmission speeds. This makes it more appropriate for next-generation IoT devices, such as Augmented Reality (AR) and Virtual Reality (VR) devices.

These days, it is hard to even imagine daily life without Wi-Fi. It is easy to forget that, just 20 years ago, Wi-Fi was not expected to become the most commonplace wireless data telecommunications technology. However, as the industry expanded to smartphone-based technology, the realization grew that Wi-Fi was the most effective method of response to today’s data traffic explosion. Thanks to the lower cost of setting up and operating — when compared to cellular networks — it is a method that is still growing exponentially.

Unlike cellular systems using infra-networks, the data link range of a Wi-Fi network can only be extended up to a few hundred meters, so it is emphatically local. In addition, as it uses unlicensed bandwidth, it can be affected by interference from other telecommunication systems, making it risky for supporting advanced Quality of Service (QoS).⁷ However, as cellular and Wi-Fi convergence technology advances, it continues to provide a huge convenience: an undisrupted user experience. All over the world, Wi-Fi has long gone beyond being seen as a specific technology and is instead treated more like a public infrastructure.

“Back in 2016, a dedicated team was set up to get Wi-Fi technology to the point where it could be integrated into the Exynos processor,” said Joonsuk Kim, Executive Vice President of the Connectivity Development Team. Kim was the team leader when the Connectivity Team was first established when joining Samsung in 2016. “In only about four to five years, we completed the development of the legacy protocols all the way up to the sixth generation of Wi-Fi (Wi-Fi 6) by achieving technological stability and readiness. Although there was not enough investment or talent, our technology caught up in just a short period of time,” he recalled.

▲ Exynos’ Wi-Fi technology nearing the market leader in only six years

After its success in developing and commercializing Wi-Fi 6E, as well as all the previous Wi-Fi protocols, Samsung Electronics is now developing Wi-Fi 7, which is targeted for next generation flagship as a discrete modem. Since Wi-Fi needs to provide connection for all mobile and IoT devices supporting the latest protocol, it is crucial that the performance of all legacy protocols is improved and maintained and that the performance of the most recent protocol is similarly secured. This latest protocol — Wi-Fi 7 — will likely be expanded to the market from 2024. It boasts the Multi-Link Operation (MLO),⁸ a channel bandwidth of 320MHz and 4096QAM.⁹ Through these capabilities, Wi-Fi 7 will have the advantages of faster data transmission speed, increased data transmission volume, improved power efficiency and the ability to support undisrupted wireless connectivity, even in an environment where users abound.

▲ The size of the Wi-Fi market is projected to grow from 4.7 billion in 2022 to 6 billion in 2027.
Source: LANCOM (Survey Digital Policy in Germany), TSR (June 2022)

In order to further enhance the fast transmission speeds of Wi-Fi, the internal processor core needs to become more complex than it currently is, and an internal memory with a large capacity is required.

“To make this happen, we are staying focused on research and development of multi-processor structures, and on securing the intellectual properties necessary for fast transmission,” Kim said. “Until now, companies in other countries have been the main players leading the development of Wi-Fi solutions. But the Wi-Fi technology of Exynos is the only Wi-Fi solution in Korea that is commercialized on a large scale. I’m confident that, when it comes to embedded Wi-Fi solutions for mobile SoC, our technology comes second to none,” Kim said.

This is important, because, when it comes to Wi-Fi, only the best is good enough for customers. Although most people, in general, do not realize how much of an advanced technology Wi-Fi truly is, they do expect to be able to access fast, uninterrupted Wi-Fi almost wherever they are.

“Many users recognize revolutions in cellular networks, such as the LTE and 5G, as advanced technologies, thanks to their advertisement as major features of phones in mobile carriers’ active marketing,” said Kim. “However, by contrast, people do not quite seem to recognize how quickly Wi-Fi technology is evolving.”

▲EVP Joonsuk Kim has been working on connectivity technology for 20 years.

However, when asked if he thinks the role of Wi-Fi will still be important in the future, Kim was resolute.

“The data transmitted through Wi-Fi these days makes up 70 to 80%¹⁰ of overall wireless data traffic,” he said. “Cellular networks and connectivity technology pursue different usage scenarios and this is not likely to change any time soon. Wi-Fi technology and cellular technology should advance together by complementing each other. As the role of information technology (IT) becomes more important in our lives, the ability to minimize dead-zones and provide stable connections and fast data services indoors will become very important for Wi-Fi technology.”

To fully tap into future technologies like augmented reality (AR), virtual reality (VR) and the metaverse, fast speed and low latency are crucial.

“Wi-Fi uses low-frequency bandwidth, such as 2.4GHz, 5GHz and 6GHz,” Kim explained. “So the diffraction is relatively higher, and this enables the fast, stable transmission of data.”

As 320MHz frequency became usable with the availability of 6GHz bandwidth, connections between devices with ultra-fast and low-latency could be achieved even faster than originally expected. Kim emphasized the role of Wi-Fi advancement in this process. At the same time, the Connectivity Development Team developed and completed the commercialization of the latest specification (BT5.2), Bluetooth and GNSS that successfully entered the Flagship by applying L5 satellite and sensor correction technology for high-performance positioning, and recently indoor positioning with accuracy within several centimeters. Kim explained that if UWB technology, which has been developed for measurement and is in preparation for its first commercial use, can be combined, it can exert strong power in many high-spec IoT services and applications in the future.

“To help our latest products lead the market standard, to secure competitiveness and sustainability in the future and to make sure stability and compatibility are achieved well in advance, I personally hope that we implement wireless access points¹¹ and enter the relevant product market to do so,” Kim said.

Protecting Your Privacy on Smartphone: Security That Strengthens a Separate Security Operation Environment (iSE)

Smartphones play a lot of roles these days. Two particularly significant such roles are identification cards and wallets. Take biometrics, mobile identification (eID) and Samsung Pay, for example. These services often require users to verify their identity, and there is always the possibility that hacking can occur in the process of user verification. As such, a level of security that goes beyond the software level is called for, which means it is required on the hardware level and even in semiconductors.

The semiconductor that provides security in smartphones is called the Secure Element (SE) semiconductor. There is a separate embedded Secure Element (eSE) located outside the SoC, but, with Exynos 2020, an integrated Secure Element (iSE) is embedded in the security block inside the SoC.

“The name we have given to the project that focuses on iSE embedded in Exynos is ‘STRONG,’ which is an abbreviation of Secure Tamper-Resistant of Next Generation,” said Jongwoo Lee, Vice President of the Design Platform Development Team. “The iSE is a separate environment within the SoC that operates security programs. The iSE plays not only the role of the eSE — which can be separately embedded on the outside — but it can control the security of the SoC as well. Advanced processing means it boasts high performance, and it also enables safe expansion to external memory, such as DRAM and Flash. These many roles can be taken even further and protect the SoC in the active security module.”

▲ (From left) Keunyoung Park from the AP S/W Development Team, VP Jongwoo Lee, PL Bogyeong Kang and Sunghyun Kim from the Design Platform Development Team are doing their utmost to strengthen the security environment in mobile devices.

The iSE is used for device security and security services. Device security is focused on strengthening the security of the device itself, and security services are focused on the information of users that is held within mobile devices, like mobile identification, payment and car keys.

“At the beginning of this year, we finished the PoC (Proof of Concept) and succeeded in developing the iSIM,¹² the most applicable service using iSE,” Lee said. “This was a result of close cooperation between Samsung Research, which is in charge of the iSE Secure OS (Camelia), and the digital security company Thales, which is in charge of developing the iSIM Secure Application.”

The iSIM is an upgraded version of the embedded SIM (eSIM) and it integrates the function of the SIM within the SoC. This provides convenience for users because it allows them to change their mobile carrier without changing their SIM card, have more than two phone numbers at once and make use of various mobile carrier services on one device. From the perspective of smartphone manufacturers, the iSIM provides advantages as well, because it lets them remove the SIM card slot and reduce the space needed for parts: iSIM can be operated within the SoC without a separate semiconductor, as is the case with discrete eSIM.

▲uSIM, eSIM and iSIM size comparison

What makes the development of the iSIM so significant is the extreme difficulty developers encounter in meeting the technological environment requirements for embedding iSIM.

“The iSIM needs to meet Global System for Mobile Communications (GSMA) requirements,” said Lee. “That means embedding the iSIM over the OS software and hardware above a certain security level, a level called CC EAL4+.¹³ However, we have hardware that operates one level higher than this guideline: CC EAL5+. We also have secure external memory where large SIM profiles can be embedded.”

“We are the only company that can provide both the eSE and iSE, which are the basis for the eSIM and iSIM,” Lee continued. “So we can provide solutions that smartphone manufacturers can easily and flexibly adopt. Personally, I believe there is no such thing as ‘perfect’ in the area of security, but we are working hard to get as close to perfect as is technologically possible. Our teams will continue to make constant effort in providing a high-level security operation environment that can accommodate the many different security features different platforms provide.”

¹ Digital communication: A method of converting an analog signal into a digital signal, transmitting it to the other party and converting it back into an analog signal that can be recognized by humans. High-quality and large-capacity communication are possible compared to analog communication.

² Mobile broadband: A technology that provides high-speed multimedia Internet services to mobile devices such as smartphones and tablet PCs.

³ New Radio (NR): A 5^th generation mobile communication technology. Consists of sub-6 GHz and mmWave (millimeter wave, high frequency band of 24-100 GHz band). Although mmWave has the advantages of ultra-high speed, ultra-low latency and super-connectivity, it has the disadvantage of poor diffraction.

⁴ Institute of Electrical and Electronics Engineers (IEEE): An American association of electrical and electronic engineers and the world’s largest technical organization.

⁵ 3^rd Generation Partnership Project (3GPP): A mobile communication standardization technology cooperation organization founded in December 1998 to establish international standards related to wireless communication, such as GSM, WCDMA, GPRS and LTE.

⁶ Ultra-Wideband (UWB): A technique that lowers maximum transmit power to less than -41.3 dBm/MHz so as not to interrupt other wireless. However, it uses wide bandwidth (500MHz) to achieve comparably high data rates.

⁷ Quality of Service (QoS): This refers to the guarantee of communication service quality, delay time or data loss rate below a certain level on the network. It also refers to a communication service level agreed or defined in advance. In other words, it is a generic term for various technologies that intelligently match the transmission demand of various applications to a given network resource by allocating network resources such as bandwidth and priority in order to send data to a destination quickly, at a constant speed and reliably.

⁸ Multi-Link Operation (MLO): The technology that operates various channels of different frequency bandwidths at the same time.

⁹ 4096 QAM (Quadrature Amplitude Modulation): A modulation method for transmitting data by shifting and adjusting the amplitude and phase of the in-phase carrier signal and quadrature-phase carrier signal. It is advantageous when a large amount of data needs to be transmitted in a narrow transmission bandwidth. 12bits per symbol in a 4096QAM

¹⁰ Source: February 22, 2019

¹¹ Wireless Access Point: The low-power wireless device that plays the role of a base station in wireless LAN. It is also referred to as a Wi-Fi extender, Wi-Fi amplifier or wireless extender.

¹² iSIM (integrated SIM): A built-in subscriber identification module. Also called ieUICC (integrated embedded universal integrated circuit card)

¹³ Common Criteria Evaluation Assurance Level (CC EAL): Common Criteria (CC) is an international standard for evaluating the security of IT products and certain websites. Evaluation Assurance Level (EAL) is a grade that is assigned to evaluation assurance.

Equipped With a Brain That Surpasses Computers: Strengthening Cooperation With for CPU

In this second series installment, Samsung Newsroom sat down with two project leaders at Samsung Electronics to better understand the role of CPU and NPU in mobile devices. A computer’s central processing unit (CPU) is often compared to the human cerebrum, the largest part of your brain that handles many responsibilities. Similarly, the CPU is the most important unit that deals with a computer’s four main functions, which are memory, decoding, operation and control. CPU is the factor that determines the overall performance of a PC. Likewise, a mobile CPU runs all software on an operating system (OS) and controls other hardware peripherals, helping a smartphone perform at its optimal level.

CPU performance is determined by a variety of factors, including the clock speed,¹ IPC² and the number of cores.³ The phones of the past were powered by a single-core CPI with a simple pipeline structure. Consequently, there were limits in handling parallel processing, and the maximum frequency only amounted to a few hundred MHz. However, the CPU in smartphones today has a superscalar⁴ structure, allowing it to execute parallel processing for various commands or instructions. Additionally, it can run at 3 GHz speed, or 3 billion cycles per second, and have eight or more multi-core structures. Mobile CPUs now have a microarchitecture that pushes the performance beyond desktop CPUs.

Exynos’ CPU has evolved from a big core to a big-little and then a big-mid-little structure to keep its size small and power consumption low. Big-little structure is a processing architecture concept that dynamically switches between two types of cores — a big and a little — to maximize performance or maximize power efficiency, depending on the task. For example, the CPU performance needed for texting versus playing a 3D game is different. Therefore, when sending a text, the process uses a smaller, power-efficient core instead of a high-performing core.

▲ Project Leader Wookyeong Jeong has worked in the CPU field for more than 20 years since joining Samsung.

“CPU determines the competitiveness of all systems, including the SoC. It’s an influential area and the top priority when it comes to developing advanced semiconductor technology,” said Wookyeong Jeong, the SoC Design Team 2’s project leader who is in charge of all tasks related to the Exynos’ CPU. Jeong has worked in the CPU field for more than 20 years since joining Samsung.

“Achieving a high performance with a limited power budget is key,” said Jeong. “It is important to operate different types of CPU cores, including big, mid and little in appropriate combinations to achieve maximum efficiency in various situations.” Exynos’ CPU optimizes a combination of activated cores to deliver users the best experience in situations requiring high performance, such as playing a game or using a camera on mobile devices.

▲ CPU Core Structure of Exynos 2200

Based on the IP of semiconductor design company Arm, Samsung Electronics is taking the performance of CPUs up a notch. When Jeong was asked about the specific tasks of the team’s developers, he explained the team’s role and responsibilities.

“We decide the performance goal for the CPU of a product, acquire the CPU IP, predict and review the performance, validate and conduct debugging⁵ before mass production and further steps. We take care of the overall development work to enhance CPU performance,” Jeong explained. “The System LSI Business is responsible for taking the RTL CPU design from Arm to create an optimal semiconductor chip,” Jeong said. “The team is also responsible for designing and creating the CPU peripheral circuit, such as an appropriate memory subsystem, for maximizing CPU performance.”

“With the adoption of Arm CPU, we have a vision of becoming the mobile industry’s best CPU manufacturer by optimizing software not only on a chip level but also on a device level. We aim to become an E2E⁶ total solution provider,” said Jeong when asked about the future development direction of the company. “To achieve this goal, the CPU developers have been working very closely with Arm, device manufacturers, Samsung Foundry and others as one team since the early development stages. In addition, they’re seeking various ways to enhance performance, such as advanced packaging technology that enhances performance further,” Jeong explained.

“With the emergence of AR and the metaverse, appropriately utilizing all processors, such as CPU, GPU and NPU for comprehensive machine learning processing on a SoC level would give us an important, competitive edge. We’re going to focus on increasing our competitiveness by strengthening the CPU’s performance in machine learning processing as well,” Jeong added.

Real, Imaginative Technology: The Advancement of NPU Based on Proprietary Technology Throughout Six Generations

An NPU is a processor optimized for deep learning⁷ algorithm arithmetic. It can process a large amount of data as fast and efficiently as the human neural network. For such reason, it is mainly used for AI arithmetic and computation. While it may seem complicated, it is already commonly used in devices. For example, thanks to NPU, a smartphone’s camera can recognize and focus based on the objects, environment and people in the frame. It can automatically switch on the food filter mode for food photography or even remove unwanted subjects in the picture.

▲ AI Remover function within new smartphone improved as NPU developed.

In the past, when NPU did not exist, GPU mainly performed AI computation. However, the computation efficiency⁸ was low due to the hardware’s structural differences. These days, the NPU is mainly in charge of AI computation, and it can process data more efficiently in mobile devices as well. It’s optimized for parallel data computing so that AI-based applications can run faster on low power.

▲ Project Leader Suknam Kwon, who has been working on the NPU since its second generation, now leads the NPU developers.

Exynos’ NPU development began in 2016. The first SoC equipped with the NPU was Exynos 9820, which was embedded in the Galaxy S10 that was released in 2019. “When the first task force was formed six years ago, we had only about 20 people, but now our team has grown tenfold if we include the members from our overseas research institutes,” said project leader Suknam Kwon. Kwon used to design the hardware of the SoC and has been working on the NPU since its second generation. “The NPU is an area of high interest these days, but back then, it was so unfamiliar and new that we had to learn from videos and university lectures overseas.”

In the past, there were few applications for the NPU, including detecting objects based on images. However, in the era of AI, market demand for high-performing IP requiring a large amount of computation is increasing. This can be used to perform tasks such as improving camera picture quality, voice services and more. In addition, since size and power consumption increase as IP performance is enhanced, determining the most efficient architecture is key.

▲ AI using cloud servers compared to On-device AI

As NPU gets more powerful, it offers improvements in object recognition speed or photo enhancement. The performance of the NPU equipped in the latest Exynos is two times more enhanced compared to previous generation. By independently developing the NPU for six product generations, the SoC Design team’s expertise and know-how in NPU technology is second to none. “With advantages in benchmark such as the ML Per, power efficiency, size, etc., Exynos’ NPU is a highly competitive IP solution,” Kwon said. “Through optimization of architecture for performance and improvements in power efficiency, the NPU adds competitive value for Exynos processor,” he said.

Going forward, the technologies that utilize NPU will continue to evolve. “I think the on-device AI, which performs AI computation in one’s smartphone rather than going through a server, will become more widely used because there is less risk of having sensitive personal information leaked,” Kwon said. “Because of this, mobile NPU performance needs to be even more enhanced. These days, one NPU is used for many computations, but I predict that there will be more demands for operating specialized AI algorithms for each application program. So, developing an NPU that is specialized for each domain will be important as well,” he added.

When asked about autonomous driving, Kwon discussed the role that NPU will play in the industry. “In the near future, the advanced driver-assistance system (ADAS) will become a reality,” Kwon said. “It requires hardware that can perform autonomous driving algorithms using a massive amount of data in real time. To accomplish this, a higher-performing NPU is needed, and Samsung is preparing an NPU with powerful capabilities for autonomous driving devices that meet the market’s demands.”

At the end of the interview, Kwon explained the most meaningful moment that occurred during development. “Each year, Exynos comes with a higher-performing NPU that is increasingly enhanced, which is very meaningful,” he said. “It will continue to become a key IP for future markets. I take a lot of pride in the fact that developing NPU has led to the growth of both myself and the company — and even contributes to the country’s overall competitiveness,” he said. “It’s the best field where it makes the things in one’s imagination come true.”

* All images shown are provided for illustrative purposes only and may not be an exact representation of the product or images captured with the product. All images are digitally edited, modified or enhanced.

¹ Clock: Continuously generates electric oscillation of 0 or 1 for computation. It’s expressed in Hz, and a higher clock figure means a faster processing speed.

² IPC (Instructions per Cycle): Instructions processed per clock. It measures the clock needed to process one command or instruction. IPC is the unit that assesses how efficiently a CPU is operating.

³ Core: The key part in the physical processing circuit within the CPU. The more cores there are, the easier it is to perform multiple actions at the same time. Single-core means there’s one core, dual-core means there are two, quad-core means there are four and so on.

⁴ Superscalar: An architecture that combines the advantages of pipeline and parallel processing and enables instructions from multiple pipelines to be processed in parallel. The processing speed is fast because multiple instructions can be executed at the same time without having to go through waiting status first. 

⁵ Debugging: A process of checking whether the designed program is accurate, identifying program errors and fixing them.

⁶ End to End

⁷ Deep Learning: Technology that enables a machine to learn, infer and reason like human beings using data.

⁸ In mobile SoC, efficiency means it uses less power or has faster speeds.

Exynos: The Technology Intensive System Semiconductor

In the first installment of this series, Samsung Newsroom shares the importance of the graphics processing unit (GPU) and image signal processor (ISP) in the Exynos mobile processor (SoC). Before meeting with the seven IP development leaders, Samsung Newsroom first met with the SoC Development Head and Senior Vice President Mingoo Kim, who oversees system-on-chip (SoC) design in the System LSI Business.

Kim first explained the fundamental reason behind the concept of SoC, in which various features are all incorporated into a single chip. “When chips are divided, it becomes difficult to manage their power consumption completely,” Kim said. “When each feature consumes power separately, the battery efficiency also decreases. In addition, the bandwidth limit and transfer time latency will affect data transmission between chips, which can lead to reduction in performance.” Consuming minimal power is very important for smartphones because, unlike desktop computers, smartphones are not continuously supplied with power.

“SoC has high efficiency due to comprehensive power control. And as a single chip, it also takes up less space within a smartphone,” Kim explained. “When all functions are performed by a single chip, performance is significantly improved.” Modern mobile phones go beyond simply sending and receiving calls and texts and have evolved to perform a multitude of advanced functions, including taking videos, mobile gaming and accessing financial services. The SoC, which is smaller than a thumb nail, has played a big role in making this possible.

As the SoC is the epitome of all main types of information technology that exist today, Kim described it as the “flower of system semiconductors.” “SoC is not an easy field to work in, but it’s an optimistic field that any engineer would aspire to become a part of,” Kim said. “The role of SoC will be limitless in future industries, such as the metaverse, autonomous driving and 6G.”

Samsung will continue to focus on developing proprietary IP, including GPUs, NPUs, ISPs, modems, RF and more. Samsung strives to take another step forward in chip design to become a platform solution company. “With our competitiveness in SoC, we aim to see Exynos recognized as the best mobile processor brand available,” Kim said. “Through this feature series, we hope the role and importance of SoC, the characteristics and advantages of Exynos as well as its developmental direction will be shared with more people.”

Expanding the Possibilities of Mobile Gaming: GPU for More Enhanced Graphics

In general, graphics processing requires large-scale computation, and it is faster and more efficient if processed in parallel (parallel processing). However, the structure of a central processing unit (CPU) is specialized for fast, serial processing. As such, graphics processing with a CPU would cause important computations to be delayed due to this constant computational performance by CPU. One example of this can be seen when playing a game. It’s possible that your character may not be able to avoid an enemy due to the touch input being delayed while graphics are being rendered on the display.

To address these issues, GPU was developed. Before there were GPUs, CPUs took care of everything. However, GPU was conceived to increase efficiency as a separate accelerator for similar computations that are frequently used. In short, CPU is like a general-purpose calculator while GPU is a large-scale parallel calculator specializing in graphics processing. This is how GPU came to be, and it is one of the key components in graphics processing. It receives commands from CPU and displays an object’s shape, location, color and texture on the monitor.

The Xclipse 920 equipped in the Exynos 2200 is the first mobile GPU Samsung jointly developed with AMD, a U.S. based global company that specializes in semiconductor products like GPU for PC and consoles. The name ‘Xclipse’ is a combination of the ‘X’ from Exynos and the word ‘eclipse.’ The name represents Samsung’s goal to go beyond the limits of mobile gaming and carry out performance on the level of console games, ushering in a new era of gaming.

▲Vice President Sungboem Park, a mobile processor design expert who oversees GPU development

In line with this, Samsung collaborated with AMD to develop a power efficient, console-level GPU for mobile devices. AMD’s GPUs are designed specifically for PCs or consoles, meaning they had to be redesigned to fit the mobile environment. Specifically, it was redesigned to accommodate the memory bandwidth of mobile, which is relatively limited, in addition to managing heat dissipation. “Based on our rich knowledge of low-power design, acquired from developing mobile SoCs, we were able to successfully achieve power efficiency and miniaturization in the first-generation product,” said Vice President Sungboem Park, a mobile processor design expert who oversees GPU development. “We focused heavily on minimizing heat, because mobile devices do not have fans like gaming consoles, while also maintaining performance so that the frames do not lag.”

The main role of the GPU in Exynos is to display objects in a 3D virtual space on a 2D smartphone screen, a role that is especially important when playing graphically demanding games on mobile devices. In particular, the Xclipse 920 is the first mobile GPU to support hardware-accelerated ray tracing (RT). Ray tracing is a technology which produces realistic lighting effects by simulating light rays reflected from 3D objects. By being accelerated by hardware rather than software, Xclipse 920 is able to perform real-time computations faster. In addition, variable rate shading (VRS) technology adjusts the amount of GPU computation depending on changes in color, shade, movement and other variables of the objects on screen to reduce GPU overload.

▲The Xclipse 920 has its own hardware support for ray tracing (RT) technology, which produces realistic lighting effects by simulating light rays reflected from 3D objects.

As the number of game users grows and graphics become more detailed, the development direction of GPU is becoming increasingly more important. This includes increasing the performance level to that of high-performance consoles while lowering battery consumption. By improving these two crucial areas, users are able to experience high fidelity graphics on mobile devices similarly to how they are experienced on consoles. “In general, mobile tends to lag around five years or so behind consoles when it comes to graphics technology, however, we were able to incorporate the latest console technologies in the Exynos 2200 mobile processor quickly through our collaboration with AMD. The SoC is applied to the Galaxy S22,” Park said. “We plan to continue to implement other features in the RDNA series by working closely with AMD going forward.”

“As the performance of smartphones has become enhanced overall, it’s true that it’s not easy to create a performance edge that is significant enough for consumers to notice,” Park answered when asked about the future direction of mobile GPUs. “From now on, the reason for flagship smartphone users to purchase the latest smartphones will most likely be dependent on gaming performance,” he said. This means that the possibility of the further advancement of GPUs, which determines a smartphone’s gaming performance, is high.

He also predicted that mobile GPUs will become even more important in the fields of AR and VR as well. “For AR, GPUs will need to be equipped in lightweight devices, such as glasses, so a low-power design is very important,” Park said. “Performance requirements are much more demanding in the field of VR, as the entire visible virtual world needs to be rendered instantly. As such, we need to satisfy various development requirements while also generating more realistic images at a much faster rate than we currently can. So, the advancement of mobile GPU is crucial going ahead and will have limitless applications,” he emphasized.

Elevating the Level of Satisfaction in Camera Performance: ISP for More Natural and Vivid Images

An ISP corrects raw data transferred from an image sensor and creates a photo or video to a form preferred by the user. ISP also corrects the potential physical limitations of a camera module — comprised of an optical system and an image sensor — interpolates red, green and blue (R/G/B) and removes noise. In addition, it carries out post processing, such as adjusting the brightness of a video and emphasizing detailed areas. Simply put, through fine tuning and post processing, ISP generates the picture or video that is most desirable by the users.

▲ Whole process of ISP in Mobile Camera

In earlier smartphone models, ISP was equipped as a separate chip. However, due to market demand, embedded ISP soon became the norm. “At first, we cooperated with research institutes overseas to develop a high-performing ISP that can be used for digital cameras,” said Jongseong Choi, a project leader (PL) in the Multimedia Development Team who has been working in the video processing field for more than 20 years. “As a result, our first embedded ISP solution was utilized in the Galaxy S4’s main camera.” Since 2012, the Exynos mobile processor has been contributing to a substantial advancement in smartphone cameras’ video image quality through the internalization of ISP, enabling performance at the level of digital single-lens reflex (DSLR) cameras.

▲Jongseong Choi, Project Leader of the Multimedia Development Team, has been working in the video processing field for more than 20 years.

With a high-performing ISP, consumers are able to enjoy higher video image quality as well as faster processing speeds. “It’s difficult to explain in specific numbers how great a photo is because photography is subjective, but we are conducting various research studies such as video evaluation using deep learning and ISP tuning technique to create natural and sharp photos and videos,” Choi explained. In addition, ISP also determines the speed of the burst rate in continuous shooting and is responsible for the fast-processing of high-resolution photos and videos.

The high-performing ISP equipped in the latest Exynos can process up to 200 million pixels. Up to seven image sensors are supported, and videos and images from up to four image sensors can be processed simultaneously. Also included is the ability to apply different parameters per each element, such as sky, bushes, skin and so on by incorporating semantic segmentation technology that recognizes the scenes being captured with the help of NPU. The AI feature detects and marks a person’s face and adjusts the brightness, focus and color of the video based on the face’s coordinates.

▲ Example of contents aware image processing using semantic segmentation

When asked about the future direction of ISP, Choi answered that development will be focused on maintaining low-power usage and improving video image quality. “The data transferred from the image sensor is processed in real-time by ISP, but the amount of data is increasing exponentially,” Choi said. “So, a significant amount of power is consumed in writing the data into memory and then in retrieving it later. ISP in Exynos, however, is designed to save data in memory only once, thereby minimizing power consumption,” he emphasized.

“The era of videos has arrived faster than expected and, because of this, we’re focusing on improving the video image quality,” Choi said. “In particular, we’re making efforts to increase our competitiveness by improving the video image quality, even those taken in dark, low-light environments.”

* All images shown are provided for illustrative purposes only and may not be an exact representation of the product or images captured with the product. All images are digitally edited, modified or enhanced.

Samsung Electronics plans to invest about KRW 20 trillion by 2028 for the complex in an area covering about 109,000 square meters within its Giheung campus. The new facility will lead advanced research on next-generation devices and processes for memory and system semiconductors, as well as development of innovative new technologies based on a long-term roadmap.

Today’s groundbreaking ceremony was attended by Samsung Electronics Vice Chairman Jay Y. Lee, President and CEO Kye Hyun Kyung, President of the Memory Business Jung-Bae Lee, President of the Foundry Business Siyoung Choi and President of the S.LSI Business Yong-In Park, along with more than 100 employees.

“Our new state-of-the-art R&D complex will become a hub for innovation where the best research talent from around the world can come and grow together,” said President Kye Hyun Kyung, who also heads the Device Solutions (DS) Division. “We expect this new beginning will lay the foundation for sustainable growth of our semiconductor business.”

With the establishment of the new R&D facility, Samsung Electronics is seeking to overcome the limits of semiconductor scaling and solidify its competitive edge in semiconductor technology.

Samsung Electronics’ Giheung campus, located south of Seoul near the DS Division’s Hwaseong campus, is the birthplace of the world’s first 64Mb DRAM in 1992, marking the beginning of the company’s semiconductor leadership.

The new Giheung R&D facility, together with the R&D line in Hwaseong and the world’s largest semiconductor production complex in Pyeongtaek, is also expected to elevate the synergy among Samsung’s three main semiconductor complexes in the metropolitan area.

After the ceremony, Vice Chairman Jay Y. Lee visited the Hwaseong campus to meet with employees of the DS Division, where they discussed ways to promote innovation within the company. At a separate meeting with executives of the DS Division, discussions involved current issues in the global semiconductor industry, progress of next-generation semiconductor technology R&D and ways to secure technology to expand semiconductor leadership.

Samsung Electronics, a world leader in advanced semiconductor technology, held its 3^rd Annual Samsung Advanced Foundry Ecosystem (SAFE^TM) Forum 2021 virtually today.

With the theme of ‘Performance Platform 2.0: Innovation, Intelligence, Integration’, Samsung and its foundry ecosystem partners prepared 7 plenary talks and 76 technology sessions focused on three main topics: Gate-All-Around (GAA, Innovation), Artificial Intelligence (AI, Intelligence) and 2.5D/3D (Integration) technologies and the diverse design infrastructures required for high-performance applications.

“In the rapidly changing data-centric era, Samsung and its foundry partners have made great strides responding to increasing customers demand and to support their success by providing powerful solutions,” said Ryan Lee, Senior Vice President and Head of Foundry Design Platform Development at Samsung Electronics. “With the support of our SAFE program, Samsung will lead the realization of the vision ‘Performance Platform 2.0’.”

Starting with a keynote live streaming on November 17, attendees are able to explore a variety of tech sessions and engage with ecosystem partners through the virtual SAFE Forum platform for a month. To register for SAFE forum, please visit https://www.samsungfoundry.com.

SAFE 2021: Performance Platform 2.0

Samsung has concentrated on expanding its foundry ecosystem by focusing on IP, Electronic Design Automation (EDA), Cloud, Design Solution Partner (DSP) and Package solutions necessary for today’s data-driven era. Samsung introduced today its latest SAFE^TM program including:

• SAFE^TM-IP & EDA: Samsung and its foundry ecosystem have reserved over 3,600 IPs and 80 certified EDA tools respectively. These are developed and verified based on the high-standard certification program run by Samsung and participated in by our partners. In order to respond to the demands of high performance applications, Samsung’s foundry ecosystem has developed not only HPC-specific foundation IPs including standard cell libraries and memory compilers but also key IPs, such as over 100Gbps Serializer-Deserializer (SerDes) interface and 2.5D/3D multi-die integration solutions.
  
  With our EDA partners, Samsung has secured design tools optimized for its unique 3-nanometer (nm) GAA process technology and design methodology for integrating multiple dies in 2.5D/3D. Customers can also utilize AI- and machine learning-based EDA technology to systematically manage and analyze design data. To overcome the increasing difficulties of chip design and analysis, Samsung has strengthened cooperation with partners to develop EDA tools and related technologies, such as incorporating GPUs that can efficiently use computing resources required for chip verification.

• SAFE^TM-OSAT: Samsung plans to lead ‘beyond-Moore’ technologies by strengthening various package line-ups such as 2.5D/3D through the expansion of its SAFE-Outsourced Semiconductor Assembly and Test (OSAT) ecosystem. The recent announcement of the co-development of Hybrid-Substrate Cube (H-Cube) solution, which offers efficient integration of 6 HBMs and cost benefit, is one of the successful examples of Samsung foundry’s collaboration with the OSAT community.

• SAFE^TM-Cloud Design Platform: SAFE^TM-CDP, the cloud-based one-stop design platform introduced last year, now supports a hybrid cloud function that can be linked to customers’ conventional design environments.

• SAFE^TM-DSP: Through the SAFE^TM-DSP ecosystem, Samsung and its global partners can actively support global fabless companies to implement their design ideas into custom product by utilizing cutting-edge process technologies as well as high-performance, low-power chip design knowledge.

[Quote from SAFE^TM Partner companies]

• Ansys, Ajei Gopal, CEO

“Today’s chips demand a full multiphysics approach, which requires engineering simulation. Ansys is proud to partner with Samsung to deliver a comprehensive multi-physics analysis flow for Samsung’s multi-die integration initiative. The benefits to joint customers, to the industry – and to the entire world – are tremendous. Semiconductors will drive innovations as varied as autonomous and electric vehicles, artificial intelligence, and mobile technologies, including 5G and beyond.”

• Arm, Simon Segars, CEO

“Our longstanding partnership with Samsung Foundry has been essential for growing business opportunities in many markets for our combined partner ecosystem. This close collaboration continues as we work together to optimize our Armv9 next-generation processors on Samsung Foundry’s leading-edge processes, including GAA, to deliver a best-in-class solution that is optimized for the world of today, and the technologies of tomorrow. Together, we are unlocking new opportunities across HPC, Automotive, AI, and IoT, while also managing rising complexities, enabling faster time to market.”

• Cadence, Lip-Bu Tan, CEO

“The Cadence Intelligent System Design strategy is very well-aligned with Samsung Foundry’s Performance Platform 2.0 with common themes of innovation, pervasive intelligence and integrated solutions. Together, we’re enabling customers to develop and deliver innovative, breakthrough products using Samsung’s most advanced process and packaging technologies, and we look forward to continuing our work with Samsung Foundry to accelerate design successes”

• Siemens EDA, A. J. Incorvaia, Senior Vice President

“The Samsung SAFE event provides an exceptionally valuable venue for the Samsung Foundry ecosystem to meet, share information and identify opportunities to fully leverage Samsung’s cutting-edge process technologies. Siemens EDA looks forward to this year’s Samsung SAFE event and the many opportunities it presents for collaborating with customers and partners to eliminate design obstacles and enhance silicon success.”

• Synopsys, Sassine Ghazi, president and COO

“We see exciting times ahead as software and chip technology come together to create world-changing new products,” said Sassine Ghazi, president and COO of Synopsys. “We have strong programs with Samsung Foundry on 3nm gate-all-around enablement, broad IP certification, AI-assisted chip design and 2.5/3D multi-die design to name just a few. We welcome the strong collaboration opportunities offered by the Samsung SAFE initiative.”

Samsung Electronics, a world leader in advanced semiconductor technology, today unveiled plans for continuous process technology migration to 3- and 2-nanometer (nm) based on the company’s Gate-All-Around (GAA) transistor structure at its 5^th annual Samsung Foundry Forum (SFF) 2021.

With a theme of Adding One More Dimension, the multi-day virtual event is expected to draw over 2,000 global customers and partners. At this year’s event, Samsung will share its vision to bolster its leadership in the rapidly evolving foundry market by taking each respective part of foundry business to the next level: process technology, manufacturing operations and foundry services.

“We will increase our overall production capacity and lead the most advanced technologies while taking silicon scaling a step further and continuing technological innovation by application,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics.” Amid further digitalization prompted by the COVID-19 pandemic, our customers and partners will discover the limitless potential of silicon implementation for delivering the right technology at the right time.”

GAA Is Ready for Customers’ Adoption – 3nm MP in 2022, 2nm in 2025

With its enhanced power, performance and flexible design capability, Samsung’s unique GAA technology, Multi-Bridge-Channel FET (MBCFET^TM), is essential for continuing process migration. Samsung’s first 3nm GAA process node utilizing MBCFET will allow up to 35 percent decrease in area, 30 percent higher performance or 50 percent lower power consumption compared to the 5nm process. In addition to power, performance and area (PPA) improvements, as its process maturity has increased, 3nm’s logic yield is approaching a similar level to the 4nm process, which is currently in mass production.

Samsung is scheduled to start producing its customers’ first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023. Newly added to Samsung’s technology roadmap, the 2nm process node with MBCFET is in the early stages of development with mass production in 2025.

FinFET for CIS, DDI, MCU – 17nm Specialty Process Technology Debuts

Samsung Foundry is continuously improving its FinFET process technology to support specialty products with cost-effective and application-specific competitiveness. A good example of this is the company’s 17nm FinFET process node. In addition to the intrinsic benefits afforded by FinFET, the process node has excellent performance and power efficiency leveraging a 3D transistor architecture. Consequently, Samsung’s 17nm FinFET provides up to 43 percent decrease in area, 39 percent higher performance or a 49 percent increase in power efficiency compared to the 28nm process.

Additionally, Samsung is advancing its 14nm process in order to support 3.3V high voltage or flash-type embedded MRAM (eMRAM) which enables increased write speed and density. It will be a great option for applications such as micro controller units (MCUs), IoT and wearables. Samsung’s 8nm radio frequency (RF) platform is expected to expand the company’s leadership in the 5G semiconductor market from sub-6GHz to mmWave applications.

Looking ahead, in cooperation with its ecosystem partners, Samsung Foundry’s SAFE Forum will be held virtually in November 2021.

For me, what is most exciting about this milestone is that it highlights how far the semiconductor industry innovations have come today and provides a glimpse into the evolutions that will shape the industry of tomorrow.

Consider that the 5nm process is here in just six months after last October’s unveiling of the first commercial application of EUV in our 7nm process. It’s a rapid progress made possible in large part by running thousands of wafer layers through EUV exposure systems each week. Hands-on experience is the only way to ascend the EUV learning curve, and that body of knowledge is growing daily.

In the learning process, we’re seeing one of the biggest and broadest benefits of EUV – the simplification of design by moving away from increasingly complex multi-patterning lithography strategies. While still early, it’s increasingly clear that the reduced number of mask steps and more straightforward process is nothing short of a revolution for silicon designers. Sighs of relief will be heard as EUV will be seamlessly incorporated into the existing design architectures.

Samsung’s 5nm is the next step in the evolution of EUV. 5nm will be more efficient and feature new innovations including Samsung’s proprietary Smart Diffusion Break (SDB) transistor architecture. One of the most important aspects of 5nm is that it supports 25 percent area reduction and 10 percent performance improvement or 20 percent power reduction than 7nm.

Also, it will be largely design-rule compatible with the existing design of 7nm. Therefore, it is essentially a recharacterization of the technology, not redesign, which will substantially reduce time and the cost of implementation. This combination of technological advance and economic advantage is very much in line with a grand tradition of the semiconductor industry.

This merging of technological advancement and economic benefits is very much in line with the grand tradition in the semiconductor industry as well as technologies including 5G, AI, Connected & Automotive, Robot, etc. – constantly serving as a catalyst for the fourth industrial revolution, while simultaneously driving costs down. That’s why the evolution-moment of 5nm is, in its own unique way, as important as the innovation-moment of 7LPP.

Bringing EUV into production has been a long, challenging process. It required substantial investment of time, money, and human resources. While there were certainly moments of doubt along the way, we had to pursue our vision. The 5nm announcement offers compelling evidence for the value of the investment. As businesses from diverse fields including Foundry, Fabless, the Design House, Packaging, Tests, etc., the semiconductor ecosystem will grow stronger. This is a new chapter for the semiconductor industry, and we are excited to be part of the continued journey in innovation.

Pioneering Automotive Solutions

Samsung’s automotive solution offering has been one of the highlights of this year’s CES, and at the Encore Hotel showcase, key components and technologies for in-vehicle infotainment, telematics and the advanced driving assistance system (ADAS) were on display to invited customers and partners.

Exynos Auto V9 is Samsung’s first dedicated automotive system-on chip for next-generation IVI (In-Vehicle Infotainment) systems. The Exynos Auto V9 can support up to six high resolution displays through powerful processing from eight core CPUs and a tri-cluster GPU, an advanced GPU arranged in three separated sets of GPU cores able to seamlessly support multiple systems simultaneously. The Exynos Auto V9 is also equipped with a neural processing unit (NPU) that processes visual and audio data to accurately recognize face, speech and gesture patterns for intelligent driving experiences. The showcase demo presented diverse concurrent driving assistant and entertainment experiences – for example, the running of navigation in the central information display (CID) at the same time as a movie plays in rear-seat displays.

Exynos Auto T is a telematics solution that empowers safe driving experiences through the integrated use of telecommunications and informatics technologies. The industry’s first cellular modem to support multi-mode from 2G to 5G NR, the Exynos Modem 5100, was also showcased.

ADAS is leading the way in in-drive visual perception capabilities. The demonstration showcased how the ADAS system can recognize and detecting all manner of objects such as cars, pedestrians and traffic signs. Furthermore, the DRVLINE, an open, modular and scalable platform for building ADAS with a faster time to market, was introduced at the showcase.

ISOCELL Auto image sensor is an advanced new solution capable of bringing about a wholly new driving experience thanks to its high performance in detecting objects in a variety of lighting conditions. The ISOCELL Auto image sensor technology provides unrivalled object recognition in a diverse range of driving environments, as the sensor’s high resolution and fast frame rate enables the accurate detection of any moving objects, while its high light sensitivity assists in object recognition even in dark lighting conditions. Furthermore, a wide dynamic range permits the sensor to respond quickly and effectively to sudden changes in brightness, as one might experience when driving in or out of dimly-lit tunnels.

Innovative Pixel Solution for Smart ADB(Adaptive Driving Beam) is the next-generation one-chip LED solution for headlamps that helps prevent glare affecting preceding and oncoming vehicles or pedestrians by automatically controlling the light distribution of a headlamp. Samsung presented this highly-specialized LED solution by demonstrating different driving situations including when a driver starts the engine, needs high or low beam, and faces preceding or oncoming vehicle.

Next-Generation Semiconductor Technologies

This year, five of Samsung’s latest semiconductor products have received recognition from the coveted CES 2019 Best of Innovation Awards – the Samsung 256GB 3DS DDR4 RDIMM, 512GB Universal Flash Storage, 3.84TB NVMe Z-SSD SZ1733, LM302S and the SSM-U Series.

Samsung 256GB 3DS DDR4 RDIMM is the industry’s fastest DDR4 and highest density memory module for next-generation enterprise server platforms, providing the finest high-density, high-performance consumer infrastructure solutions with extremely low-power consumption (15 watts at 1.2V).

Samsung 512GB Universal Flash Storage is the industry’s first 512-gigabyte embedded Universal Flash Storage (eUFS) for automotive A/V systems and next-gen flagship mobile devices, using Samsung’s new 64-layer 512-gigabit V-NAND chips. The 512GB eUFS package transfers a 5GB-equivalent full HD video clip to an SSD in about six seconds, over 8 times faster than a typical microSD card.

Samsung 3.84TB NVMe Z-SSD SZ1733 offers a new level of storage for supercomputing targeted for AI analysis, big data and IoT applications, using Samsung’s new Z-NAND chips which provide 10 times higher cell read performance than 3-bit V-NAND chips.

Samsung LM302S is the most user-oriented next-generation lighting platform to date, designed to improve work efficiency by helping users achieve a better circadian rhythm and healthier sleep. Its human-centric LED solution can improve a person’s concentration level for greater work efficiency by as much as 10% and improve sleep quality by repressing melatonin during the day.

Samsung SSM-U Series is a new type of smart module made up of tiny radar-based sensors with higher detecting sensitivity than conventional sensors. The SSM-U series features invisible and intelligent motion detection-based transmission for greater flexibility and reactivity in smart residential lighting.

To help make this spring extra special, the centers, known for their strict protocols and security, organized their first official photo contest. Held from April 6 to May 3, the contest offered employees across four Samsung semiconductor campuses a chance to soak in the sun, admire blooming cherry blossoms, and share snapshots of the beauty that surrounds them every day.

Take a look at some of the contest’s standout submissions below.

“Canola Flowers, Pinwheels and Onyang” by Myeong-ho Lee

Budding flowers are a sure sign that spring has finally come. Viewers of this vibrant image of canola flowers and pinwheels may be surprised to learn that it was snapped not on Korea’s picturesque Jeju Island, but at Samsung’s Onyang Campus.

“Symphony of Spring” by Dae-young Kim

Dae-young Kim’s photograph, captured while strolling around the Hwaseong Campus at lunchtime, depicts rows of beautiful tulips lining a tranquil stream in front of the campus’s cafeteria.

“Cherry Blossom Road” by Sang-hun Kim

For Sang-hun Kim, the contest offered an excellent opportunity to enjoy the spring weather with colleagues. One day, when crossing the cherry blossom tree-lined road that leads to the Onyang Campus’s dormitory, Kim was reminded of the iconic cover of the Beatles’ “Abbey Road” album.

Inspired, Kim returned to the crosswalk with his colleagues to snap a fun, Abbey Road-esque photo. His usual route to work had instantly transformed into a scenic setting for an unforgettable shot.

“Spring, Colorful Pinwheels, and Us” by Sang-hun Kim

Elsewhere on the Onyang Campus, colleagues pose for a playful photo amongst pinwheels spinning in the warm spring breeze.

“Smiles in Spring” by Young-ho Shin

Employees at the Onyang Campus are all smiles as they pause for a photo beneath blooming cherry blossoms. As you can see from their beaming smiles, the team is enjoying the relaxing time together.

“Let’s Run Together” by Youngjong Yoon

Each spring, the Giheung and Hwaseong Campuses organize their annual employee fun run, the Spring Race for Love. Proceeds from the race go toward efforts to enrich the campuses’ respective communities. A Giheung Campus employee Youngjong Yoon captured this candid shot of race participants using his camera.

“Beautiful R&D Center” by Il-jin Shin

For Il-jin Shin, the all-glass exterior of the Onyang Campus’s R&D Center proved the perfect canvas for capturing the beauty of a bright spring sky.

“Building Flowers” by Il-jin Shin

Here we have another submission from Il-jin Shin, taken in front of the Onyang Campus’s TP Center. The bright pastel colors adorning Buildings 1, 2 and 3 reminded Shin of spring flowers in bloom.

“Night View of MR 1 Building at Hwaseong Campus” by Hyeon-gang Heo

The photo contest showcased the unique and creative perspectives of Samsung employees.

Light trails created by car and bus headlights symbolize the dynamic nature of Samsung’s semiconductor business. It took Hyeon-gang Heo quite a bit of time to find the perfect moment to take the photo. However, as he notes, the end result was well worth the wait.

“Line 17 at Night” by Dong-jin Lim

Lastly, we have the contest’s grand prize-winning entry, captured by Dong-jin Lim at the Hwaseong Campus. The image depicts two employees as they head back to work at the Line 17 building – the campus’s latest production facility.

The summer heat may be on its way, but the talented individuals at Samsung’s semiconductor manufacturing sites will continue to greet each day with the zeal of spring, and do their part to help usher in a brighter future.

“Samsung’s ISOCELL image sensors have made great leaps over the generations, with technologies such as ISOCELL for high color fidelity and Dual Pixel for ultra-fast autofocusing, bringing the smartphone camera ever closer to DSLR-grade photography,” said Ben K. Hur, vice president of System LSI marketing at Samsung Electronics. “With an added DRAM layer, Samsung’s new 3-stack ISOCELL Fast 2L3 will enable users to create more unique and mesmerizing content.”

Conventional image sensors are constructed with two silicon layers; a pixel array layer that converts light information into an electric signal, and an analog logic layer that processes the electric signal into digital code. The digital code is then sent via MIPI interface to the device’s mobile processor for further image tuning before being saved to the device’s DRAM. While all these steps are done instantaneously to implement features like zero-shutter lag, capturing smooth super-slow-motion video requires image readouts at a much higher rate.

Delivering an advanced solution, the Samsung ISOCELL Fast 2L3 is a high speed 3-stack CMOS image sensor designed with the company’s two-gigabit (Gb) LPDDR4 DRAM attached below the analog logic layer. With the integration, the image sensor can temporarily store a larger number of frames taken in high speed quickly onto the sensor’s DRAM layer before sending frames out to the mobile processor and then to the device’s DRAM. This not only allows the sensor to capture a full-frame snapshot at 1/120 of a second but also to record super-slow motion video at up to 960 frames per second (fps). With 960fps recording, which is 32 times the typical filming speed (30fps), recording moments such as a child hitting his or her first game-winning homerun, a baby taking his or her first step, or a friend doing a gazelle flip on a skateboard becomes much more dramatic.

In addition to super slow motion video, fast readout can hugely enhance the photography experience. Since the sensor captures an image at very high speeds, it significantly reduces the ‘jello-effect,’ or image distortion, when taking a picture of fast-moving objects, for example helicopter rotor blades. By storing multiple frames in the split of a second, the sensor can support 3-Dimensional Noise Reduction (3DNR) for clearer pictures when shooting in low-light, as well as real time high-dynamic-range (HDR) imaging, and detect even the slightest hint of movement for automatic instant slow-motion recording.

The image sensor is also equipped with Dual Pixel technology, which allows each and every one of the 12-million pixels of the image sensor to employ two photodiodes that respectively work as a phase detection auto-focus (PDAF) agent. With ultra-fast auto-focus in any lighting condition, it will be harder to miss capturing important moments before they pass by.

The Samsung ISOCELL Fast 2L3 is currently in mass production.

Here, we explore exactly what EUV is and why it is so integral to developing next-generation chips.

What is EUV?

In the semiconductor industry, EUV refers to extreme ultraviolet lithography, a technology that is expected to bring a radical progress to one of the most important steps in semiconductor manufacturing, photolithography.

When producing semiconductor chips, silicon-based round disks, called “wafers” are coated with a light-sensitive substance and enter a system called a “scanner.” Inside the scanner, a laser light source is cast onto the wafers to create patterns of circuitries, which later are used for forming billions of ultrafine, microscopically small structures, inside a semiconductor chip. This process, while described very concisely, is known as photolithography.

Photo of a tall, box-shaped EUV scanner (courtesy of ASML)

With EUV technology, an EUV system, or EUV scanner, will now be able to perform the photolithography step by utilizing a light source with an “extreme ultraviolet” wavelength. In the world of chip manufacturing, realizing finer circuits is a must, as it enables integration of a greater number of components inside a chip and therefore building faster and more energy efficient chip.

The utilization of an EUV light source will allow for defining finer and denser patterns than previous methods because of its shorter wavelength, which is essential since light isn’t able to directly define features smaller than its own wavelength. Upcoming EUV scanners will, specifically, utilize EUV radiation at a 13.5-nanometer wavelength, less than 1/10th of what current ArF excimer laser scanners are able to provide.

How will EUV be implemented?

Today, semiconductor chips are being used in almost every electronic device imaginable, and EUV technology will be utilized to produce the most advanced semiconductors for mobile, server, network and supercomputing applications.

For its part, Samsung plans to utilize EUV starting with its 7-nanometer LPP (Low Power Plus) process, a cutting-edge technology that the company expects to apply by the second half of 2018. Samsung’s new fabrication line in Hwaseong, which will be ready for production in 2020, will also be set up with EUV technology to provide leading-edge semiconductor products to global market.

Samsung Electronics, a world leader in advanced semiconductor technology, has announced today its continued commitment to first-pass silicon success for its foundry customers’ chip designs by launching the Samsung Advanced Foundry Ecosystem (SAFE^TM) program.

The SAFE^TM program ensures deep collaboration between the Samsung Foundry, ecosystem partners, and customers to deliver competitive and robust System on Chip (SoC) designs based on certified key design components including Process Design Kit (PDK), reference flows with Design Methodologies(DM), Intellectual Property (IP), and ASIC design support.

“We are very excited to provide the comprehensive, collaborative, and qualified Samsung Advanced Foundry Ecosystem to our customers to enable faster and more reliable SoC design success”, said Jong Shik Yoon, executive vice president of Foundry Technology Development at Samsung Electronics. “Together with our SAFE^TM partners, Samsung Foundry will provide certified design enablement solutions to existing strategic customers as well as innovative, new start-up customers. We welcome all current and future Ecosystem partners to join the new SAFE^TM program.”

The SAFE^TM program is based on three pillars :

• EDA/DM : Provides extensively tested PDKs and reference flows (with design methodologies) that are backed by Samsung Foundry’s certification.
• IP : Provides a full set of silicon qualified, application specific IP offerings from the early stage of process technology development. Customers can view a full list of IP solutions offered through SAFE^TM by accessing Samsung Foundry’s B2B site, CONNECT(https://www.samsungfoundry.com).
• Design Services : Connects mid- to small-sized companies with qualified ASIC design services and support. Using design service partners of SAFE^TM, customers will benefit from easy access to process technology information, competitive price conditions, and committed resources for their SoC design success.

For more information about Samsung Foundry, please visit https://www.samsungfoundry.com

Quotes from SAFE^TM  Partner Companies

• Arm, Gus Yeung, vice president and general manager of Physical Design Group

“The Samsung Advanced Foundry Ecosystem creates significant opportunities for the industry. Through our ongoing collaboration with the Samsung Foundry, we are enabling the ecosystem with access to leadership co-optimized physical IP solutions for enhancing next-generation SoC designs.”

• AlphaHoldings, Donggi Kim, CEO

“It’s honor to be one of the initial member of SAFE. As a Korean design service partner, we are ready to support Samsung Foundry’s ASIC customers more effective way based on long-term collaboration with Samsung Foundry and competencies – leading edge process experiences, customer specific IP, high quality manpower, error free design capabilities, etc.”

• Cadence, KT Moore, vice president, product management

“We’ve collaborated with Samsung Foundry for many years to enable our joint customers to achieve their aggressive design goals. We believe that the new SAFE foundry design program will facilitate innovation and help customers deliver designs to market even faster. Our support for Samsung Foundry’s process technologies continues to expand with our broadened IP portfolio and full EDA tool enablement with comprehensive reference flows.”

• eSilicon, Hugh Durdan, vice president, strategy and products

“Through our Tier 1 ASIC work with Samsung Foundry, we understand Samsung Foundry’s advanced process technologies well. This allows us to offer differentiating IP targeted at the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets using these advanced process technologies.”

• Faraday, Steve Wang, President

“Samsung Foundry provides the most competitive grand ecosystem for the leading edge technologies. Since our establishment in 1993, Faraday has successfully delivered more than 2,200 ASIC mass production projects. Thus we are confident in our ability to leverage the SAFE program, targeting next-generation applications now and beyond.”

• Mentor, Joe Sawicki, vice president, Design to Silicon

“Mentor is proud that it has been the signoff solution for Samsung’s own design efforts over the last two decades and Samsung Foundry since the foundry was launched in 2005. We are pleased to be continuing our close partnership with Samsung as it expands its ecosystem interactions via the Samsung SAFE initiative.”

• Rambus, Luc Seraphin, senior vice president and general manager, Memory and Interfaces Division

“As ASIC and SoC designs continue to increase in complexity, high-speed interfaces are integral to successful design. This strong partnership between Rambus and Samsung across multiple nodes, ensures that we are providing a broad portfolio of high-quality solutions to our end customers. We are pleased to collaborate with Samsung Foundry to provide designers with leading high-speed SerDes and memory PHY IP solutions for easy integration into their chip designs.”

• Synopsys, Deirdre Hanford, co-general manager, Design Group

“Our collaboration with Samsung Foundry since 2005 has enabled mutual customers to deliver state-of-the-art designs across a wide range of Samsung’s process technologies. The SAFE program will help accelerate adoption of Synopsys’ high-quality IP, market-leading tools, and comprehensive design services supporting Samsung Foundry for development of their differentiated SoCs.”

• VeriSilicon, Wayne Dai, President and CEO

“Our experience in shipping high volume SoCs using Samsung 14nm and 10nm FinFET, as well as 28nm FD-SOI process demonstrates that Samsung Foundry has excellent potential for the China market. Now as a charter member of SAFE, we will expand our partnership to a new level enabling us to better support our mutual customers.”

Take SIM cards, electronic IDs, e-passports and credit cards. One thing they all have in common is the fact that they all use smart card ICs. Samsung has been an important part of the movement to this ubiquity of the technology as the industry switches from older, less secure solutions such as magnetic strip cards.

For example, Samsung has led the SIM card market since 2006. And in 2013, Samsung was the first in the industry to be accredited with a CC EAL7 smart card IC, the highest level of security certification. The company will continue to expand here and elsewhere in the smart card IC market in the future thanks to the value-added solutions it is incorporating into its products, such as embedded Secure Element (eSE) or embedded flash.

[Samsung’s S3FT9MF smart card IC]

Expansion Based on Robust Security

The Samsung S3FT9MF smart card IC supports both ISO7816 contact and ISO14443 contactless interfaces, and is CC EAL6+ (Common Criteria Evaluation Assurance Level) certified, providing strong security countermeasures against various security threats such as template attacks, power attacks and reverse engineering.

Strong security and durability are of utmost importance when it comes to smart card ICs that hold extremely personal and private information. With a high level of security and a fast yet durable embedded flash solution with up to 500,000 write/erase cycles, Samsung’s smart card IC will continuously keep users’ personal information safe and sound in various forms of smart cards.

Samsung’s most recent smart card IC, S3FT9MF, is the solution for payment cards issued by financial institutions, such as Swiss banks, and has been expanding the smart card IC business to government IDs and other payment applications. The S3FT9MF is steadily being adopted as the main IC by several clients recently including a European tier-1 card manufacturer. Also, electronic IDs equipped with Samsung’s S3FTM9F are expected to become available in the first half of 2018.

Changing Standards

Traditional magnetic strip cards have been the de-facto solution for ID and payment cards since the 1960’s but concerns rose as the static information on the strips could easily be cloned. Smart card ICs have recently become an alternative solution with their stronger security attributes, as well as the versatility of the technology.

Such benefits of the smart card ICs have driven the transition to EMV (Europay, Mastercard, Visa; the global standard for payment cards with smart card ICs) cards in developed countries as well as the expanding adoption of e-passports and government-issued IDs. In the government ID sector alone, market estimates show an average of seven-percent in annual growth in quantity for smart card ICs from 2015 through 2022.* And as the market grows, Samsung is ready to expand.

* Source: ABI Research (2017 Q2)

Coming to work may be a daily grind, but it helps if the walk to the office is a pleasant stroll. What also helps is that, under a few ground rules, employees use flexible working hours, making it easier to manage work-life balance.

Semiconductors are fabricated in “cleanrooms,” where the environment is strictly managed to keep internal conditions, such as temperature, humidity and air pressure, at a constant level. Such measures are optimized for the ever-shrinking chips being manufactured, today mostly designed in nanometer (nm) scale, as well as for the workers inside.

Given the fact that 10nm is about one 10,000th the width of a single strand of hair, even a particle in few-cubic-micrometers could easily damage the circuits on our advanced chips. Workers wear “smocks” to prevent particles from being released into the cleanroom and would go through an air shower before entering the area. Even special paper and pens are required to take notes in there.

One of the key initiatives that go in tandem with efficient manufacturing is the safety of our workers on site. More than 500 safety professionals on staff oversee everyday operations and conduct regular inspections to ensure that all of our facilities comply with the most stringent regulations, locally and globally.

Every team within the company is required to train at least one of its members as an emergency care agent. The agents receive 16 hours of training on emergency response, including life-saving techniques such as CPR (cardiopulmonary resuscitation) and the Heimlich maneuver.

Employees are also trained to put out fires. As shown above, new hires begin safety training when they are initially hired and continue on a monthly basis throughout their careers based on a custom-curated curriculum.

Of course, there is a lot of research, development and other day-to-day businesses that go on but it’s also vital for us to stay active. Several sports fields around campus as well as an indoor stadium are very popular with more than 160 inter-company sports clubs’ activities, company events and performances.

Even at tech companies, often the question of the day is what to have for lunch. Calories and sodium levels of each plate are displayed on the menu so that employees can make healthy and informed decisions about their diet.

The 12 cafeterias at the Giheung and Hwaseong campuses run 24-7, with up to 20 menu selections a day from all corners of the world that would tickle any palette.

A walk after lunch is an excellent way to start the afternoon. More than 600,000m² of greenspace is managed in Giheung and Hwaseong campuses combined, an area equivalent to more than 75 soccer fields.

A coffee break under a tree is just as refreshing. More than 60,000 trees in Giheung and Hwaseong campuses include numerous species such as pine, oak, ginkgo and elm, which provide the perfect shade to cool off.

Employees can also look after their health by working out at one of the several gyms across campus that are equipped for weights, treadmill, swimming, pilates, squash and climbing. About 4,000 employees per day use the gyms regularly.

Personal trainers are also available on site to help you work out the muscles you didn’t know you had.

In case of the unfortunate event of feeling under the weather, employees can drop by the healthcare center on site for primary care from physicians, dentists, dermatologists, acupuncturists, pharmacists and counselors on staff. Physical therapy, musculoskeletal treatment and regular health checkup services are also available.

Samsung Electronics has been a major player in the semiconductor industry since the early ‘80s and has strived to deliver advanced technologies that bring meaningful changes to our everyday lives.

In this two-part series, we will take a closer look at our semiconductor operations in Giheung and Hwaseong in Korea, where most of its state-of-the-art semiconductors are developed and made.

Samsung’ Semiconductor Business has recently seen unprecedented success, largely owing to surging demand in advanced memory products for both consumer and enterprise, as well as a diversified IT landscape with critical drivers such as IoT, automobiles and AI.

The shift towards these data-intensive and hyper-connected platforms has spurred expanded investments in data centers, enterprise servers, network systems and HPC (high-performance computing) that require the highest level of performance and energy efficiency in large capacities. Samsung’s high-capacity memory solutions such as DRAM, V-NAND SSDs and HBM2 (high bandwidth memory) address this growing trend while mobile memory solutions with fast and efficient V-NAND technology continue to power today’s smart mobile devices.

Along with Samsung’s memory chips, CMOS (complementary metal-oxide-semiconductor) image sensors are also among the S.LSI business’ flagship products for Samsung. Its proprietary ISOCELL® technology separates each pixel with a physical barrier that hugely boosts image quality and enables smaller pixels. Consumer demand for DSLR-quality pictures and dual-lens cameras are spurring growth in the high-performance image sensor market. In addition to image sensors, display driver ICs (DDI), mobile processors and connectivity solutions also add to the business’ comprehensive product portfolio.

Our legacy all began with this—the 64Kb DRAM. About a decade later since its establishment in 1974, Samsung’s semiconductor business made its first mark in the industry with the chip. Its development narrowed the technology gap with industry forerunners from ten years to four. In 1992, Samsung became the top DRAM manufacturer with the development of the 64Mb DRAM and rose as the top memory manufacturer the year after.

Before there were smartphones, we flipped through phone books to look up a contact. Just when Samsung’s very first semiconductor was being developed, these company phone books from 1983 and 1984 “stored” valuable information that connected our organization. Just like the smartphones today, these fit comfortably in the pockets.

At the heart of the Giheung Campus is the Administration Building (left), Line 1 (right) and Line 2 peeking through in between, where Samsung’s semiconductor history began in the mid-‘70s. The Admin building and Line 2 stand as they did more than 30 years ago while Line 1 was rebuilt for upgrades.

In front of the Administration building stands the Muhantamgusang (Statue of Infinite Study) since Day 1 of Samsung’s semiconductor business. The statue symbolizes founder Byung-chul Lee’s vision and mission for the business, and the spirit of continuous curiosity, research and study is at the core of Samsung’s operations. The bronze statue was commissioned to sculptor Se-Jung Kim, who is famous for his statue of Admiral Yi Sun-sin in Seoul’s Gwanghwamun Plaza.

The most recent addition to Samsung’s production lines in Korea is Line 17 in the Hwaseong Campus adjacent to Giheung. Since its opening in 2016, the line has been manufacturing logic chips for foundry customers along with DRAM. The Foundry Business has successfully been producing the industry’s first 10-nanometer (nm) mobile processor since earlier this year and is diversifying its product lineup to IoT, automobiles, home appliances and PCs.

One of the advantages of Samsung’s semiconductor manufacturing sites is that they are in clusters, which allows not only quick decision-making and real-time management around the clock but also tool sharing between manufacturing lines that maximize the efficiency of its resources. The bridge between fabrication lines shown above is an example of this kind of flexibility.

Approximately 23 percent of the industrial water used for Samsung’s semiconductor operations is recycled at wastewater treatment facilities as shown above. Internal pollutant discharge standards are set 30 percent lower than the law requires, and discharged water temperatures are strictly controlled to minimize the impact on the ecosystem and redirect the heat for energy reuse.

Semiconductor fabrication uses a variety of chemicals in large amounts which demand strict and safe management of these materials. Samsung’s Central Chemical Supply System (CCSS) is where chemicals used in manufacturing are stored and supplied to their destination. Supply systems are enclosed within chambers equipped with local ventilation as a safety precaution.

All piping and joints at the CCSS are doubled and sealed in case of any leakage.

The CCSS are monitored 24-7 in real time for chemical input/output as well as any abnormalities such as shortage, leakage or spill.

Semiconductor technologies are moving ahead at light speed, but that doesn’t mean that we are exempt from the responsibility to ensure that the technologies and materials we use are safe. Before a new chemical substance is introduced, it is analyzed for physical and chemical characteristics, potential health hazards and any associated risks. We also established the Samsung Health Research Institute, a research organization to safeguard healthy working environments, improve employees’ well-being and raise the standard for assessing workplace health and safety.

Semiconductors have been a major precursor to the growth of the IT industry and will continue to inspire innovation in the digital devices of tomorrow. To sustain its edge in the IT landscape, Samsung opened the Device Solutions Research (DSR) center in 2014 to spur collaboration and collective synergy among its semiconductor research and development teams working on numerous projects. The complex is comprised of three 27-story towers and is currently home to more than 10,000 employees.

It is no secret that innovation cannot be done alone. The Samsung-SAP Research Center (SSRC) within DSR is an example of Samsung’s collaborative efforts and open partnerships with a wide spectrum of industry innovators. Shown above is one of SSRC’s test servers, SAP HANA (High-performance Analytic Appliance), for in-memory platform development. With 24TB of memory based on 128GB TSV and NVMe SSDs, as well as hardware/software optimization support, this database server solution has the muscles to test next-generation systems especially for banking, enterprise and national defense.

As we move forward to the fourth industrial wave, Samsung’s semiconductor business continues to push boundaries and looks ahead for the next technological leap that will fundamentally change our way of life and enrich our everyday experiences.

“Samsung started mass production of its 28FDS process technology last year and reached the desired process maturity earlier than originally scheduled,” said Ryan Lee, Vice President of Foundry Marketing at Samsung Electronics. “So far we have taped out more than 40 products based on the FD-SOI process for various customers. With the addition of RF and eMRAM on 28FDS and 18FDS technologies, we expect an increasing number of product engagements.”

Samsung eMRAM is the newest addition to the family of embedded non-volatile memories and it offers unprecedented speed, power and endurance advantages.

“By adding only three layers in the back-end of the process, we can simply integrate the new eMRAM cells into the existing baseline FD-SOI process,” said Gitae Jeong, Senior Vice President of the Advanced Technology Development Team at Samsung Electronics. “Combined with Samsung’s memory technology leadership and its differentiated FD-SOI technology, we finally succeeded in incorporating eMRAM into various commercial applications”

“Samsung is working with NXP on a test chip to deliver eMRAM macro capability which is optimized for embedded processor integration and manufacturing.” said Ron Martino, VP and GM for NXP’s iMX Applications Processor product line. “This test chip is complete and will produce results in the 4^th quarter. This work will further enable the vision of integrating diverse SOC components on a single SOC in a cost effective manner.”

Samsung has completed its full set of 28FDS technology eco-system solutions with various eco- system partners including Cadence and Synopsys. Customers can access Samsung certified 28FDS reference flows from Cadence and Synopsys along with application-specific IP offerings.

“Through our collaboration with Samsung, our mutual customers can access the 28FDS certified, comprehensive Cadence RTL-to-GDS reference flow,” said KT Moore, vice president, product management in the Digital & Signoff Group at Cadence. “The Cadence tools integrate the back-biasing and multi-bit flip-flop design optimization features included with the Samsung 28FDS process technology, enabling designers to quickly and easily develop high-quality SoCs with optimal power and performance.”

“Early joint collaboration on PDKs, reference flows and IP is a hallmark of the Samsung/Synopsys relationship,” said Michael Jackson, corporate vice president of marketing and business development for the Design Group at Synopsys. “For Samsung’s 28FDS, our mutual customers can design with confidence, knowing that it has been fully certified for Synopsys’ Design Platform and Design Ware® IP.

Details on the recent updates to Samsung Foundry’s cutting-edge process technology including FD-SOI technology roadmap and readiness will be presented at the Shanghai FD-SOI Forum on September 26^th, 2017, by ES Jung, Executive Vice President and General Manager of Foundry Business at Samsung Electronics.

Samsung Electronics, a world leader in advanced semiconductor technology, today announced a successful network processor tape-out based on Samsung’s 14LPP (Low-Power Plus) process technology in close collaboration with eSilicon and Rambus. This achievement is built on Samsung’s cutting-edge foundry process and design infra for network applications, eSilicon’s complex ASIC and 2.5D design capability with its IP solutions, and Rambus’ high-speed 28G SerDes solution.

Samsung’s 14LPP process technology based on 3D FinFET structure has already been proven for its high performance and manufacturability through mass production track record. The next generation process for network application is 10LPP process which is based on 10LPE (Low-Power Early) of which mass production was started from last year for the first time in the industry. 10LPP process’ mass production will be started in this year end.

Additionally, Samsung named its newly developed full 2.5D turnkey solution, which connects a logic chip and HBM2 memory with an interposer, as I-Cube^TM (Interposer-Cube) solution. This 14LPP network process chip is the first product that Samsung applied I-Cube^TM solution together with Samsung’s HBM2 memory. The I-Cube^TM solution will be essential to network applications for high-speed signaling, and it is expected to be adopted into other applications such as computing, server and AI in the near future.

“I am delighted to announce 14nm network processor tape-out,” said Ryan Lee, Vice President of Foundry Marketing Team at Samsung Electronics. “This successful product tape-out was combined with eSilicon’s proven design ability in network area and Rambus’ expertise in SerDes and Samsung’s robust process technology along with I-Cube solution. This collaboration model is very unique solution which will have very big impact in network foundry segment. Samsung will keep developing its network foundry solution to be a meaningful total network solution provider aligned with its process roadmap from 14nm and 10nm to 7nm.”

“This project was a true collaboration between Samsung, Rambus and eSilicon. eSilicon is proud to bring its FinFET ASIC and interposer design skills along with our substantial 2.5D integration skills to the project,’” said Patrick Soheili, Vice President of Product Management and corporate development at eSilicon. “Our HBM Gen2 PHY, custom flip-chip package design and custom memory designs also helped to optimize the power, performance and area for the project.”

“Networking OEMs are looking for high-quality leadership IP suppliers that can bring 28G backplane SerDes in advanced FinFET process nodes to market,” said Luc Seraphin, senior vice president and general manager of Rambus Memory and Interfaces Division. “Our success with Samsung and eSilicon is a testament that these industry-leading solutions are attainable when you bring leading companies together. This is the first of several other offerings we plan to bring to networking and enterprise ASIC markets around the globe.”

*Tape out(T/O): The last step in designing a new chip. By the time of the tape-out, the photo-mask of a chip is completed, and is then ready to be sent to a foundry.

“Samsung is a bellwether for Austin. As a company that the community and state partnered with to relocate here several years ago, they have far exceeded expectations,” said Mike Rollins, President, Austin Chamber of Commerce. “Samsung remains a shining example of what happens when we create a business friendly environment.  The result is a win that enhances and sustains our community’s ability to create a broad range of new jobs and economic opportunities for Austinites and their families.”

According to an Impact Data Source Economic Impact Study, SAS added $3.6 billion into the regional economy of central Texas in 2015. During that same time, SAS supported 10,755 jobs in the area and $498 million in annual salaries. Since its establishment in 1997, Samsung has invested more than $16 billion for the expansion and maintenance of its Austin facility.

“I was glad to discuss this with Samsung when our trade delegation visited Korea, and I’m thrilled that this plan is coming to fruition,” said Austin Mayor Steve Adler. “Samsung is so often a source of good news in Austin whether it’s about jobs, education, workforce development, housing or helping the homeless. Samsung is a great partner for Austin’s present, and this announcement tells us that they’ll be an even bigger part of our future.”

“We are committed to Austin and our contributions to the community,” said Catherine Morse, General Counsel and Senior Director of Public Affairs at SAS. “This is our home and we want to ensure our community is healthy and prospering. These investments will support this, while also ensuring our customers’ growing needs are met.”

Samsung Electronics, a world leader in advanced semiconductor technology, today announced that it has begun mass production of the Exynos 7 Dual 7270. It is the first mobile application processor (AP) in the industry designed specifically for wearable devices with 14-nanometer (nm) FinFET process technology. It is also the first in its class to feature full connectivity and LTE modem integration.

Since 2015, Samsung has been leading the industry in expanding the adoption of 14nm technology for a wide variety of products from premium smartphones to entry-level mobile devices. With the Exynos 7270, the company also introduces the benefits of this cutting-edge technology to wearables.

“The Exynos 7270 presents a new paradigm for system-on-chips (SoC) dedicated to wearables,” said Ben K. Hur, Vice President of System LSI Marketing at Samsung Electronics. “Designed on our state-of-the-art process technology, this AP offers great power savings, 4G LTE modem and full connectivity solution integration, as well as innovative packaging technology optimized for wearable devices. It is a ground-breaking solution that will greatly accelerate wider adoption of wearable devices by overcoming limitations in current solutions such as energy usage and design flexibility.”

Powered by two Cortex^®-A53 cores, the Exynos 7270 makes full use of the 14nm process, delivering 20 percent improvement in power efficiency when compared to its predecessor built on 28nm, and thus notably extending the battery life. By integrating Cat.4 LTE modem, the new AP allows wearables to connect to a cellular service as a stand-alone device. Tethering and data transfer between devices is also possible with its embedded WiFi and Bluetooth connectivity. In addition, integrated connectivity capabilities support FM (frequency modulation) radio, and location-based services with GNSS (global navigation satellite system) solutions.

As well as the implementation of the advanced 14nm FinFET process, Samsung’s innovative packaging technology, SiP(system-in-package)-ePoP(embedded package-on-package), enables the Exynos 7270 to feature outstanding performance and energy-efficiency within a compact solution optimized for wearable devices. The technology combines the AP, DRAM and NAND flash memory chips as well as the PMIC (power management IC) together into a single package. The solution can offer more features than its predecessor in the same 100-square-millimeter (mm²) area while reducing the height by approximately 30 percent. This gives more room for device manufacturers to design high performance, ultra-slim wearable devices.

To expedite the development process, a reference platform comprised of the Exynos 7270, NFC (near field communication) and various sensors is currently available for device manufacturers and customers.

For more information about Samsung’s Exynos products, please visit www.samsung.com/exynos

Samsung Electronics, the world leader in advanced memory technology, announced today that it has begun mass producing the industry’s first 10-nanometer (nm) class* , 8-gigabit (Gb) DDR4 (double-data-rate-4) DRAM chips and the modules derived from them. DDR4 is quickly becoming the most widely produced memory for personal computers and IT networks in the world, and Samsung’s latest advancement will help to accelerate the industry-wide shift to advanced DDR4 products.

Samsung opened the door to “10nm-class DRAM” for the first time in the industry after overcoming technical challenges in DRAM scaling. These challenges were mastered using currently available ArF (argon fluoride) immersion lithography, free from the use of EUV (extreme ultra violet) equipment.

Samsung’s roll-out of the 10nm-class (1x) DRAM marks yet another milestone for the company after it first mass produced 20-nanometer (nm)** 4Gb DDR3 DRAM in 2014.

“Samsung’s 10nm-class DRAM will enable the highest level of investment efficiency in IT systems, thereby becoming a new growth engine for the global memory industry,” said Young-Hyun Jun, President of Memory Business, Samsung Electronics. “In the near future, we will also launch next-generation, 10nm-class mobile DRAM products with high densities to help mobile manufacturers develop even more innovative products that add to the convenience of mobile device users.”

Samsung’s leading-edge 10nm-class 8Gb DDR4 DRAM significantly improves the wafer productivity of 20nm 8Gb DDR4 DRAM by more than 30 percent.

The new DRAM supports a data transfer rate of 3,200 megabits per second (Mbps), which is more than 30 percent faster than the 2,400Mbps rate of 20nm DDR4 DRAM. Also, new modules produced from the 10nm-class DRAM chips consume 10 to 20 percent less power, compared to their 20nm-process-based equivalents, which will improve the design efficiency of next-generation, high-performance computing (HPC) systems and other large enterprise networks, as well as being used for the PC and mainstream server markets.

The industry-first 10nm-class DRAM is the result of Samsung’s advanced memory design and manufacturing technology integration. To achieve an extremely high level of DRAM scalability, Samsung has taken its technological innovation one step further than what was used for 20nm DRAM. Key technology developments include improvements in proprietary cell design technology, QPT (quadruple patterning technology***) lithography, and ultra-thin dielectric layer**** deposition.

Unlike NAND flash memory, in which a single cell consists of only a transistor, each DRAM cell requires a capacitor and a transistor that are linked together, usually with the capacitor being placed on top of the area where the transistor rests. In the case of the new 10nm-class DRAM, another level of difficulty is added because they have to stack very narrow cylinder-shaped capacitors that store large electric charges, on top of a few dozen nanometer-wide transistors, creating more than eight billion cells.

Samsung successfully created the new 10nm-class cell structure by utilizing a proprietary circuit design technology and quadruple patterning lithography. Through quadruple patterning, which enables use of existing photolithography equipment, Samsung also built the core technological foundation for the development of the next-generation 10nm-class DRAM (1y).

In addition, the use of a refined dielectric layer deposition technology enabled further performance improvements in the new 10nm-class DRAM. Samsung engineers applied ultra-thin dielectric layers with unprecedented uniformity to a thickness of a mere single-digit angstrom (one 10 billionth of a meter) on cell capacitors, resulting in sufficient capacitance for higher cell performance.

Based on its advancements with the new 10nm-class DDR4 DRAM, Samsung expects to also introduce a 10nm-class mobile DRAM solution with high density and speed later this year, which will further solidify its leadership in the ultra-HD smartphone market.

While introducing a wide array of 10nm-class DDR4 modules with capacities ranging from 4GB for notebook PCs to 128GB for enterprise servers, Samsung will be extending its 20nm DRAM line-up with its new 10nm-class DRAM portfolio throughout the year.

*10nm-class denotes a process technology node somewhere between 10 and 19 nanometers, while 20nm-class means a process technology node somewhere between 20 and 29 nanometers.

**Samsung’s achievements in 2014 were about DDR3 and DDR4 products that used 20-nanometer process technology, which should be distinguished from 20nm-class process technology. The company’s first 20nm-class DRAM product actually came out three years earlier. In 2011, Samsung initiated production of 20nm-class 2Gb DDR3, and the year after, started producing a full line-up of DRAM product family that included 20nm-class 4Gb DDR3 and 4Gb LPDDR2 based packages and modules.

***Quadruple patterning is a multiple patterning technology that is used in high-end integrated circuit (IC) manufacturing, especially in the photolithography process. There are many different ways of deploying a multiple patterning technology, but the common goal is to extend the patterning resolution and enhance the feature density beyond that of conventional lithography.

****Dielectric materials are characterized by very low electrical conductivity in which an electric field can be sustained with minimal leakage. In semiconductor manufacturing, dielectric materials are used in many different steps. A major application of dielectric materials in Samsung’s 10nm-class DRAM manufacturing is to insulate capacitors and prevent electric leakage, which will result in a significant increase in capacitance and higher cell performance.

Samsung Electronics, a world leader in advanced semiconductor technology, announced its newest 12 megapixel (Mp) image sensor for smartphones, which will elevate the quality of mobile phone pictures. Already in mass production, this 1.4μm-pixel-based image sensor is equipped with Dual Pixel technology that has been reserved for DSLR cameras. The technology enables rapid auto-focus for fast photo shooting while producing premium image quality on mobile devices, even in low light situations.

“With 12 million pixels working as a phase detection auto-focus (PDAF) agent, the new image sensor brings professional auto-focusing performance to a mobile device,” said Ben K. Hur, Vice President of Marketing, System LSI Business at Samsung Electronics. “Consumers will be able to capture their daily events and precious moments instantly on a smartphone as the moments unfold, regardless of lighting conditions.”

Samsung’s new image sensor with Dual Pixel technology employs two photodiodes located on the left and right halves of a pixel, while a conventional image sensor dedicates less than five percent of its pixels, with one photodiode each that converts light particles into measurable photocurrent for phase detection. As each and every pixel of the Dual Pixel image sensor is capable of detecting phase differences of perceived light, significantly faster auto-focus has become possible. With such groundbreaking improvements, the image sensor ensures clear and sharp images especially for moving objects even in poor lighting conditions.

The image sensor has also adopted Samsung’s ISOCELL technology, which isolates the photodiodes in each pixel with a physical wall to further reduce color cross talk, maximizing the image sensor’s performance.

For top-of-the-line performance while keeping the size to a minimum, the new image sensor is built with cutting-edge chip-stacking technology. The Dual Pixel image sensor stacks a 65 nanometer (nm) sensor and 28nm logic chip together to deliver outstanding photo-taking experiences in today’s sleek smartphones.

The Audi Progressive SemiConductor Program is designed to make the latest semiconductor technologies available in cars, while increasing reliability, with the aim of intensifying the role and engagement of semiconductor companies in the process. Based on the strategic partnership, Samsung will provide its latest leading-edge memory products including 20-nanometer LPDDR4 DRAM and 10-nanometer class eMMC (embedded multimedia card) 5.1 to Audi’s future infotainment, dashboard and ADAS (Advanced Driver Assistance Systems) automotive applications.

“It is an exciting moment to offer our industry leading memory solutions to embrace the rapidly growing automotive industry,” said Dr. Kinam Kim, president of Semiconductor Business at Samsung Electronics’ Device Solutions Division. “Based on this partnership, Samsung will bring various benefits and advanced user experience to the global automotive market while providing high quality memory products with excellent performance and enhanced reliability.”

“Samsung is leading memory technology development with its high-performance, high-density DRAM and NAND flash memory solutions based on the industry’s most advanced process technology”, said Ricky Hudi, Executive Vice President Electronic Development at Audi. “Through the PSCP strategic partnership with Samsung, Audi will utilize Samsung’s high speed memory products to provide the best user experience to our customers. Both parties are committed to achieving the quality levels that people expect from the Audi brand”.

According to a recent report by Gartner, the global automotive semiconductor market is expected to grow from US $31.2 billion in revenue to US $32.7 billion in 2016 approximately, while the automotive memory market portion will reach a 4.6% percent share or about US $1.5 billion in 2016. The PSCP collaboration will illustrate next generation car applications at the highest safety and comfort level with enhanced reliability as well as improved performance, and will strengthen Samsung and Audi’s competitiveness in the global automotive industry.

A semiconductor, as you’ve learned before, is a device that can shift between a conductor and a nonconductor, hence its name. In other words, it can allow electricity to flow, or keep it from flowing, whenever necessary.

In order for a TV to turn on, what must be done? It needs to be plugged into a power outlet, of course. The same goes for semiconductors, which is where the metal interconnect process comes into play.

Laying down metal highways that bring semiconductors to life

Utilizing metal’s conductive properties, the metal interconnect process creates metal circuits along the pre-designed patterns. The metal used for semiconductor manufacturing must meet the following requirements:

1. Adhesiveness to the semiconductor substrate (wafer):
The metal needs to easily and strongly adhere to the semiconductor substrate in thin film form.

2. Low electric resistance:
Since the metal circuits deliver the electric current, the substance must have low electric resistance.

3. Thermal and chemical stability:
It is important that the attributes of the metal do not change during the metal interconnect process.

4. Easy formation of patterns:
Regardless of the quality of the metal, it is essential that the material can easily form patterns, especially during the etching process.

5. High reliability:
With the advancement of integrated circuit technology, the metal interconnect material needs to be durable even in minute scale.

6. Manufacturing cost:
Even if the above conditions are met, the cost also has to be suitable for the mass production of semiconductors.

The metals typically used in semiconductor manufacturing that meet the above criteria are aluminum (Al), titanium (Ti) and tungsten (W).

Now, let’s find out how the actual metal interconnect process is carried out.

Popular metals for the interconnect process

Aluminum, one of the main substances used in metal interconnect for semiconductor manufacturing is known to have two merits: great adhesiveness to silicon dioxide and high processability.

Because aluminum and silicon tend to react with each other, aluminum circuits on semiconductors that are made of silicon may get damaged. To prevent this, a barrier metal is deposited.

Aluminum circuits are created through deposition. When a mass of aluminum is boiled in a decompressed vacuum chamber, the chamber gets filled with aluminum particles. A wafer is then inserted into the vacuum chamber, where the aluminum particles adhere to the wafer and form a thin film. Because aluminum is vaporized and deposited in a high-vacuum environment, this is called the evaporator process. Physical vapor deposition (also known as sputtering) using plasma is also a method widely used today.

A contact is a point where a basic element and a metal interconnect meet. Should the contact be in the form of a narrow tunnel and is difficult to fill, tungsten then comes into play. In such cases, the metal interconnect process is carried out using chemical vapor deposition (CVD) instead of the evaporator process, so as to uniformly deposit the metal as a thin film.

As continued advancements are made in semiconductor technology, semiconductor fabrication processes are also experiencing changes. The metal interconnect process that we discussed today is undergoing a transition from evaporator to chemical vapor deposition so as to better meet the demands of finer design rules. Replacing traditional metals, copper is becoming the material of choice for semiconductor fabrication, thanks to its cost-effectiveness and better conductivity properties.

So there you have it. We have now covered all of the essential processes to design and build the semiconductor circuits on a silicon wafer.

In the next part of our series, we will explore the final step of semiconductor manufacturing, the testing and packaging process, in which silicon wafers are transformed into the individual chips that we see in electronic devices. Stay tuned!

In Korean, http://samsungsemiconstory.com/183.

If you get a chance to see a cross section of a semiconductor chip under a high-resolution electron microscope, you will see layer after layer of materials piled up like a skyscraper.

To fabricate such structures, the photolithography and etching processes (which we discussed previously), along with a few others, are repeated a few hundred times until layers of thin film material result in a semiconductor chip.

Today, we will be going over this “thin-film process,” in which a semiconductor chip gets its electrical properties.

Too thin for seein’

The dictionary defines a film thinner than 1 micrometer (μm, one millionth of a meter) as “thin film.” This thickness cannot be manufactured mechanically.

In order for a semiconductor chip to get the desired electrical properties, materials at atomic or molecular levels are densely piled up in the thickness of a thin film. This film is so thin that very elaborate and precise technology is required for it to be deposited evenly on the wafer.

Let’s say we are forming a 1 micrometer-thick film on an 8-inch (200mm) wafer. This would be the equivalent to evenly piling up sand 1mm thick on a schoolyard that is 200m large in diameter. Pretty high-tech, huh?

Deposition: Air-brushing with chemicals

Semiconductor deposition structure

Deposition refers to a series of processes where materials at atomic or molecular levels are deposited on the wafer surface as a thin layer to contain electrical properties.

The deposition methods can be largely divided into physical vapor deposition (PVD) and chemical vapor deposition (CVD).

Physical vapor deposition (PVD) is mainly used for depositing thin metal films and does not involve chemical reactions.

Chemical vapor deposition (CVD) occurs as particles from the chemical reaction of gas are deposited in the form of vapor activated by an external energy source. CVD can be used on conductors and nonconductors, as well as semiconductors.

For this reason, CVD is more commonly used in today’s semiconductor manufacturing processes. The CVD method is further broken down into thermal, plasma-enhanced and optical CVD depending on the source of external energy used. Plasma-enhanced CVD, in particular, yields many benefits as it can be processed at lower temperatures in large volumes while offering greater control over thickness uniformity, making it a preferred method of choice these days.

The thin film fabricated through the deposition process can be categorized into metal (conducting) layers for electrical connections between circuits, and dielectric (insulating) layers that electrically isolate the internal layers or protect them from contaminants.

For semiconductors to develop electric properties, a process of implanting ions on the deposited layer must follow. Ion implantation is the process of implanting electrically charged particles onto a semiconductor surface with circuit patterns. These ions are referred to as “impurities” and include boron (B), phosphorus (P) and arsenic (As). By inserting impurities into the wafer surface in the form of fine gas particles to a desired depth, the silicon wafer acquires its electrical conductivity. (Review the diffusion process to learn more about implanting impurities.)

Today, we looked at how the initially pure, nonconductive silicon wafer is transformed into a semiconducting wafer through the deposition and ion implantation processes. Just how thin and evenly the layer is formed during this deposition process can determine the final chip’s quality.

Stay tuned for the next part of our series, coming next week!

In Korean, http://samsungsemiconstory.tistory.com/172.

An art in itself

Etching is a method widely used in print-making for illustrations that require elaborate and detailed lines. Rembrandt, known as “the master of light and shadow,” and Goya, a leading artist of the late 18^th century, both used etching techniques in their artwork.

In etching, an anti-corrosive material is coated on a metal plate, then carved out with sharp tools like scribes and needles to draw the desired design. The plate is then dipped in a corrosive material such as nitric acid, and the level of corrosion is controlled. The exposed area is etched away, while the remaining area remains intact.

The Etching Process

Similarly, the etching process in semiconductor fabrication uses a liquid or gas etchant to selectively remove unnecessary parts until the desired circuit patterns are left on the wafer surface. By repeating this process on multiple layers, a semiconductor chip is eventually born.

The two fundamental types of etchants are liquid-phase (“wet”) and plasma-phase (“dry”), and the method used depends on which material is to be etched. Whereas engraving utilizes sharp tools to physically carve out patterns, etchants are used in semiconductor manufacturing to remove the undesired portion of the wafer while the circuit patterns are protected with an anti-corrosive layer formed during the photo process.

Compared to the wet etching technique, dry etching is more costly and complicated. However, with continued innovation in semiconductor technology and the circuitry now in nanoscale, dry etching is the more widely used technique, as it produces a higher yield.

Dry etching to rid of unnecessary parts

So how does dry etching remove the unnecessary substrate materials?

Dry etching, also called plasma etching, starts with the generation of plasma. Plasma is a state of matter —along with solid, liquid and gas— that consists of a large number of free electrons, ions and neutrons, or molecules in the form of ionized gas. When something is ionized, it means a neutron or molecule has changed its state of electrical charge by either losing or gaining electrons.

The Generation of Plasma

When a magnetic field is applied to gas, its free electrons become energized and start bumping into neighboring neutrons or molecules. This collision, or ionization, of free electrons and neutrons produces even more free electrons.

This chain reaction of ionization, called the avalanche effect, causes the number of ions to increase exponentially, resulting in a plasma state. A radical atom dissociated from this plasma state becomes volatile and moves itself away from the wafer surface, consequently peeling off surface material that was not previously coated and protected with photoresist.

There are a couple of things that we need to pay special attention to during the dry etching process.

The first is to maintain uniformity of the etching speed throughout the wafer’s surface. If the time it took to etch varies in different areas of the wafer, then there will be inconsistencies in the etch depths. This could lead to malfunctioning chips or chips containing differing properties in certain areas.

The second is etch rate, which refers to the amount of surface material removed in a given amount of time. Etch rate can differ depending on the number of reactive atoms and ions, as well as the amount of energy the ions carry which causes the surface reaction to occur.

In addition, selectivity and profile are also considered to be important elements of dry etching. All these factors must be closely controlled so as to improve the overall yield.

Now you know a bit more about the etching process that constructs the circuit patterns of semiconductors. In the next part of our series, we’ll take a look at how a semiconductor wafer gets its electrical properties.

In Korean, http://samsungsemiconstory.com/152.

Before people began to take pictures with digital cameras or smartphones, there were analogue film cameras.

Drawing a circuit on a wafer via the photolithography—or ‘photo’ for short—process is quite similar to taking a picture and having a film developed. Let’s take a closer look.

Designing circuits and creating a mask

The first step is to use computer-aided design (CAD) software and devise the circuits to be drawn onto the wafer. The size of this electronic circuit pattern can measure anywhere between 10 to 50 meters wide. This vast canvas bears a precisely designed, complex pattern that will end up on the semiconductor chips, which are about the size of a fingernail. Before this is carried out, an engineer actually steps onto the blown-up version of drawing to examine whether each part of the circuit is properly designed. The scale and the level of meticulousness required to accomplish this are quite amazing.

After examination, the pattern design is duplicated onto a glass substrate made of ultra-pure quartz with a beam of electrons, also known as an e-beam. A patterned substrate called a photoreticle, more commonly known as a photomask, which works like a negative film, is born.

Throughout the manufacturing process, the microscopic circuit has zero tolerance for any particles. As the patterned mask, which is larger than the actual chip size, passes through a reducer lens to transfer the design onto the chip, any particles that may be present on the mask could be shrunk as well. As such, particle contamination can be a significant problem during semiconductor manufacturing.

Picture-perfect technology

The photolithography process got its name from its role to transfer the circuit design onto a wafer by exposing the patterned mask to light. Making a replica on a wafer is like printing a black-and-white negative on light-sensitive paper.

Since the main focus of semiconductor technology is to scale the circuitry as small as possible, the first step to success is determined by the edge in photo process technologies. This is why continuous research in the photolithography field is a must to stay ahead.

Let’s take a closer look.

1. Making the wafer surface into a photographic print

First, photoresist (PR; highly sensitive to light) is applied evenly over the wafer surface. The additive can either be positive or negative depending on its reaction to light. Areas with positive photoresist are removed during the developing process when exposed to light, while those with negative photoresist remain. In other words, they create the image in the opposite way.

The PR layer needs to be thin, even and highly sensitive to ultraviolet rays to get the desired results.

2. From film to print

The next steps are comparable to the process for developing photographs. After a wafer is prepared with the PR layer, it then goes through the stepper where the circuit design on the patterned mask is projected and transferred onto it with ultraviolet light. Due to the scale in semiconductor manufacturing, the area exposed to light is highly controlled and selective.

As developing solutions come in contact with the photoresist, certain areas are selectively removed to create the final pattern.

As such, our circuit designs are nicely traced onto the wafer.

Stay tuned for the next part of the series, where we will see how currents run through the microscopic circuits.

In Korean, http://samsungsemiconstory.tistory.com/136.

A reliable oxide layer that shields the wafer’s surface

Before it can be used as a raw material for the integrated circuit, silicon extracted from sand goes through a purification process and is shaped into an ingot. This conic object is then cut to a uniform diameter, polished and eventually becomes a wafer.

The polished wafers start out pure in a non-conductive state. To make them semi-conductive, various substances are transferred onto the wafer, and then the circuit pattern is etched onto the surface.

Oxidation, the groundwork for the sequential procedures mentioned above, is a process in which a thin layer composed of various materials is deposited. The technique forces oxygen, or vapor, to diffuse into the wafer surface at high temperatures between 800 and 1200°C so that a thin, smooth layer of silicon dioxide can be created.

This layer protects the surface from chemical impurities and pollutants that permeate during the processes. Even tiny contaminants invisible to the naked eye can alter resistivity or conductivity and consequently damage the circuit’s electrical properties. Therefore, shielding the surface from these substances with a protective layer is crucial.

Oxides that protect the silicon surface

The silicon dioxide layer doubles as a trustworthy guardian against unintended adulteration during the ion implementation stage, and as an insulator that separates each part of the electrical circuit on the wafer to prevent a short circuit.

So what kind of chemical reaction creates this dependable oxide layer?

When exposed to oxygen in the atmosphere or within chemicals, an oxide layer begins to build on the wafer’s surface, just as iron (Fe) rusts when it becomes oxidized in the air.

There are a variety of oxidation methods, such as thermal oxidation, electrochemical anodic oxidation and plasma-enhanced chemical vapour deposition (PECVD). Among them, the thermal oxidation procedure performed at a high temperature is most widely used.

Thermal oxidation can be either wet or dry. Dry oxidation only uses oxygen to forge a thinner layer, whereas wet oxidation uses both oxygen and vapour to fashion a thicker layer.

Although oxides created by the dry method have excellent electronic properties, they grow much slower when compared to the wet method. Under identical time and temperature conditions, the wet method can present an outcome that is five or ten times thicker than that of the dry method.

This brings us to the end of the second part of the series. Stay tuned for Part 3, as Samsung Tomorrow will explain next week how the circuit pattern is imprinted on the oxide-clad wafer.

In Korean, http://samsungsemiconstory.com/110.

Although an integrated circuit (IC), also known as a semiconductor chip, may deceive you with its fingernail-sized form factor, it is actually packed with billions of electronic components—transistors, diodes, resistors, and capacitors—which all work together to perform logic operations and store data.

So, what does it take to manufacture this kind of circuit, you ask?

The technology behind engineering an IC goes far beyond the simple assembling of individual components. In fact, microscopic circuit patterns are built on multiple layers of various materials, and only after these steps have been repeated a few hundred times is the chip finally complete.

Today, we are introducing a new series that will walk you through the entire manufacturing process of this advanced device, from the raw material stage to the final testing of the semiconductor chip. The series will consist of eight parts and will be published weekly.

Read on for the first part of the series, which introduces the “canvas” for integrated circuits, otherwise known as the silicon wafer.

What’s a wafer?

A wafer, also called a disc, is a thin, glossy slice of a silicon rod that is cut using specific diameters. Most wafers are made of silicon extracted from sand. The main advantage of using silicon is that it is rich in supply, being the most abundant element in nature, just after oxygen. Its environmentally friendly properties are an added bonus.

Building an ingot, the foundation for wafers

Once silicon is extracted from sand, it needs to be purified before it can be put to use. First, it is heated until it melts into a high-purity liquid then solidified into a silicon rod, or ingot, using common growing methods like the Czochralski (chokh-RAL-skee) process or the Floating Zone process.

Ends cut off from silicon rods, or ingots

The popular Czochralski method uses a small piece of solid silicon (seed) which is placed in a bath of molten silicon, or polycrystalline silicon, and then slowly pulled in rotation as the liquid grows into a cylindrical ingot. This is why the finished wafers are all round discs.

Giving new meaning to the term “wafer-thin”

Before it is completely cooled, the cone-shaped ends of the ingot are cut off while the body is sliced into thin wafers of uniform thickness with sharp diamond saw blades. This explains why an ingot’s diameter would ultimately determine the size of a wafer. In the early days of the semiconductor industry, wafers were only three inches in diameter. Since then, wafers have been growing in size, as larger wafers result in more chips and higher productivity. The largest wafer diameter used in semiconductor fabrication today is 12 inches, or 300mm.

Smoothing things out – the lapping and polishing process

Sliced wafers need to be prepped before they are production-ready. Abrasive chemicals and machines polish the uneven surface of the wafer for a mirror-smooth finish. The flawless surface allows the circuit patterns to print better on the wafer surface during the lithography process, which we will cover in a later posting.

Know your wafer

Each part of a finished wafer has a different name and function. Let’s go over them one by one.

1. Chip: a tiny piece of silicon with electronic circuit patterns

2. Scribe Lines: thin, non-functional spaces between the functional pieces, where a saw can safely cut the wafer without damaging the circuits

3. TEG (Test Element Group): a prototype pattern that reveals the actual physical characteristics of a chip (transistors, capacitors, resistors, diodes and circuits) so that it can be tested to see whether it works properly

4. Edge Die: dies (chips) around the edge of a wafer considered production loss; larger wafers would relatively have less chip loss

5. Flat Zone: one edge of a wafer that is cut off flat to help identify the wafer’s orientation and type

This brings us to the end of the first part of the series. Want to know what happens next? Then, stay tuned for Part 2, as Samsung Tomorrow will take you through the disc production stage by discussing the oxidation process of the wafer next week.

In Korean, http://samsungsemiconstory.com/95.

Samsung’s Semiconductor Series Part 3

Building state-of-the-art semiconductor chips is one thing but making them into the actual square chips we’re familiar with involves a lot of high-tech, too. This process is called packaging, or back-end manufacturing, where chips are essentially sliced off of the silicon wafer, wired up and encased in epoxy for protection.

Let’s say you have a nice order of milkshake that you want to chug down right now. Organic ingredients with crush-ins of your liking, whatever floats your boat. For that, you would need an efficient apparatus (a.k.a. big enough straw) that can deliver a satisfactory flow of sips, preferably an insulated cup that will keep the frothy integrity of the beverage and temperature-resistant nerves that can hold up to the huge amount of milkshake intake against a massive brain freeze. Similar elements and materials are taken into consideration when chips are packaged. Well, okay, it gets way more complicated with semiconductors, but you get the point.

With the amount of data that need to be processed and the speed that is required today, we want to make sure we offer device manufacturers and consumers the total package, in every sense of the phrase, so that the packaging complements the advanced silicon technology inside. This would also determine the size of the final chip. So yes, packaging solutions, even for semiconductor chips, does matter.

Here are some cool examples of Samsung’s approach to this technology.

Through Silicon Via (TSV) – We talked about increasing cell density on a single chip for higher capacities but another way to achieve that is to stack individual chip dies in a single package. In doing so, the dies are ground from the back as thin as possible, down to several micrometers, so as to minimize the height of the final product.

Instead of the traditional method of connecting the stacked dies externally, we can now pierce hundreds of tiny holes through DRAM dies and then vertically connect them through the holes, allowing faster data processing with less power consumed. This means that if data were in a building, it can just take the elevator downstairs instead of working its way out to the fire escape. Remember, we’re still working in microscopic scales.

TSV allows approximately twice the speed with about half the power compared to packages using the traditional wire bonding. Again, less space, less power consumption and faster data — another reason our DDR4 DRAM using TSV are so awesome.

Read more: Samsung Electronics Starts Mass Production of Industry’s First 8-Gigabit DDR4 Based on 20 Nanometer Process Technology

ePoP – Sleeker mobile devices mean scarcer space for components, so consolidation is very much desired. As such, even chips with different functions can get bundled together and we’ve seen packages come in forms of eMMC (embedded multi-media card: NAND+controller), eMCP (embedded multi-chip package: DRAM+NAND) or PoP (package on package: AP+DRAM). Samsung’s broad chip portfolio encompassing DRAM, NAND and AP, as well as our advanced packaging capabilities in-house, has naturally given us a huge advantage in this department.

Wonder why there aren’t any packages mentioned above incorporating NAND memory and APs? An active AP can get as hot as 80 to 100℃ whereas NAND would normally get ‘fried’ at that temperature. Because of NAND’s low resistance to heat, it’s been considered that it cannot be in the same package as the AP.

Well, guess what — with an out-of-the-box approach and some new techniques, earlier this year, Samsung was able to introduce the industry’s first ePoP (embedded package on package) memory that can be stacked directly on top of an AP.

Our ePoP memory packs a LPDDR3 DRAM and an eMMC together, dramatically shrinking traditional area configurations by about 40 percent. Thanks to its efficiency and small footprint, Samsung’s ePoP memory is now finding itself on board of wearables as well as high-end mobile devices.

Read more: Samsung Electronics Mass Producing High-Density ePoP Memory for Smartphones

Samsung’s Semiconductor Series

Read Part 1. The Itsy-Bitsy Mighty Chip in a Great Big Digital World 

Read Part 2. Physics Busting at Its Seams

Samsung’s Semiconductor Series Part 2

Read Part 1 

Semiconductors have been in a race to drive up both product performance and process manufacturing efficiency. Enter the mobile era, the market clamored for smaller and more powerful devices that would make the most out of their battery life. As the inside of such devices became prime real estate, components had to follow suit.

The convention was to shorten the distance between the circuitry. That means faster data transfers that require less energy, has more compact configurations and yet has the same capacity became possible. Fabrication productivity also got a boost as technology generations progressed.

While market needs catalyzed innovation and aggressive scaling in semiconductors, bringing digital experiences into the palms of our hands, chip fabrication methods quickly ran into a whole bunch of walls—or the lack of them. With details shrinking down to the billionth of a meter, it came to a point where traditional materials wouldn’t work anymore, electric charges started leaking and signals were getting crosstalk. In other words, scaling down the technology any further would gravely compromise the information being stored or waste the energy being consumed.

Our engineers couldn’t really defy the laws of physics. But they were able to bring about new designs and fabrication expertise in semiconductor technology that opened up meaningful opportunities for the industry.

14nm FinFET AP (application processor) – A warm and gooey marshmallow between two graham crackers is good enough as it is but if you make your s’more ‘denser,’ the crackers are brought closer together and the marshmallow gets squished up. That’s kind of what happened with the channel structures of transistors for FinFET. And no, the channel did not ooze out.

In February, we came out with the industry’s first mobile application processor (AP) based on advanced 14nm FinFET technology. By raising a ‘fin’ over the conducting channel and wrapping it over with the gate, the new structure addresses the problems of current leakage, or short-channel effect, that comes with finer technologies, while demonstrating greater power advantages and performance levels over our previous 20nm process technology. With our 14nm FinFET AP out in the hands of consumers, we’re staying busy prepping for 10nm FinFETs and beyond.

Read more: Samsung Announces Mass Production of Industry’s First 14nm FinFET Mobile Application Processor

20nm DRAM (Dynamic Random Access Memory) – For decades, the semiconductor industry had followed the pattern of doubling the density of ICs (integrated circuit) every two years. But delivering new technology refined enough for mass production got painstakingly harder. Due to limitations especially in the current technology of drawing crazy-thin lines, namely the lithography process, the 25nm design rule is where the industry thought to be the limit for DRAMs. It had been so for nearly two years. We were stuck.

Then, in 2014, came a breakthrough. Bleeding-edge methods such as modified double patterning and atomic layer deposition were introduced, heralding the arrival of the industry’s first 20nm DRAM. Contrary to common belief, we were able to utilize existing lithography tools, keeping costs viable as well. Not only was this a major breakthrough, but it also paves the way for sub-20nm nodes. We are currently the only manufacturer with this technology and are offering a full DRAM lineup for PC and enterprise systems as well as mobile device customers.

Read more: Samsung Electronics Starts Mass Production of Industry’s First 8-Gigabit Mobile DRAM

3D V-NAND (NAND flash memory) – Let’s say you have a single-story dormitory that you sectioned off for a number of occupants. You needed to accommodate more people, so rooms got smaller and the walls thinner. But tiny dorm rooms with thin walls are no fun at all. So what do you do? You build a skyscraper instead and give each of your tenants the entire floor, of course. All of a sudden, you don’t have to be fighting for space anymore and even better, everybody’s happy and much more productive. Voilà, 3D V-NAND flash memory.

Samsung is the first and still is the only company providing V-NAND products, which feature vertically stacked NAND flash cells. The technology marks a major milestone in memory technology as it overcomes the scaling limitations for conventional 2D planar structures, as well as drastically mitigating development time and resources. Even the first generation V-NAND demonstrated at least twice and up to ten times the reliability while also doubling its write performance. And don’t worry; a few dozen additional cell layers won’t affect the thickness of the final chip at all. Our second generation V-NAND products have also been very well received in the market, especially for applications in today’s SSDs that are equipped for the most demanding tasks.

Read more: Now I know my three-bit three-dee vee-nand ess-ess-dee [Editorial]

ISOCELL (CMOS image sensors) – Between pixel size and image quality, there always was a delicate balance to maintain. A good image sensor will capture as much light, or photons, as possible, as accurately as possible through individual pixels within the sensor array. Theoretically, more pixels and larger sensor size would guarantee better picture qualities. However, we’re living in a mobile world. Since smaller pixel sizes come at the expense of the amount of light received, increasing the light sensitivity of each pixel has been the focus of image sensor development so far. Another problem with size; as pixels got packed closer together, photons that had been absorbed would wander into adjacent cells, making pictures blurry or diminishing color fidelity.

Introduced in 2014, our proprietary solution, ISOCELL, was to form a physical barrier between neighboring pixels so that more light is absorbed into the pixels correctly. This results in sharper and richer picture quality. The walls also create a wider chief ray angle (CRA) that reduces the height of the module. In other words, the pixels can afford to be less deep since they can capture those little photons hitting the pixel at a wider angle that would otherwise wander off to the pixel next door. All of these qualities make ISOCELL image sensors ideal for today’s compact devices.

Read more: Get the Big Picture: CMOS Image Sensors and ISOCELL

“Innovation” may probably be one of the most over-used buzz words of our generation. It seems that we encounter ‘innovation’ daily.  In defense of those in the IT world, though, it’s just testament of how fast technologies are evolving. Their life cycles are getting increasingly shorter and breakthroughs are getting that much more difficult to come by. The good news is that engineers are innate problem-solvers, and thanks to them, technology continues to move forward, even in semiconductors down at the nanometer (nm; one billionth of a meter) scale.

In this three-part series, we’ll explore the feats in the semiconductor industry and how Samsung Electronics has tackled some of the most mind-boggling challenges in chip technology.

Datacenters that actually have to shoulder most of the job will increasingly have a hard time keeping up with this snowballing trend. About 3.1 zettabytes (ZB) of data traffic went through datacenters globally in 2013**. By 2018, that amount is expected to nearly triple to 8.6 ZB. On top of the sheer amount of data to be processed, the need for electricity and space for these facilities also climb up. If these trends continue, industry calls for some serious innovation from hardware at the system level all the way up to consumer devices.

Taking the charge in rewriting the way we process data is no small undertaking. But it’s something that we, Samsung Electronics, actually can be bold enough to dare. Not only do we offer awesome consumer electronics, but we also have the cutting-edge component solutions up our sleeves—the very chips that hum behind the scenes of our data-driven world. To us, this is our innovation. And we’re pretty serious about it.

The advancements of today’s electronic devices have become more interesting than ever and semiconductors have risen as heroes of this progress. But it’s a little-known fact that Samsung has been a veteran in this field for more than 40 years. In fact, Samsung has been the leading memory manufacturer since 1993 (that’s 23 consecutive years!) and are the second largest semiconductor company in the world. Today, Samsung is the only company that offers a comprehensive portfolio of component solutions spanning from DRAM and NAND flash memory, logic products such as mobile application processors (AP), CMOS image sensors (CIS), display driver ICs (DDI), near field communication (NFC) chips to LED light sources, just to name a few.

Earlier in February this year, Dr. Kinam Kim, Samsung’s Semiconductor Business president and IEEE (Institute of Electrical and Electronics Engineers) fellow, talked about “silicon technologies and solutions for the data-driven world” in his keynote during the ISSCC (International Solid State Circuit Conference) in San Francisco. Dr. Kim addressed the crowd of eager engineers in the audience on the advancements and opportunities in chip technology. Although he spoke mainly about the developments within the industry at large, Samsung’s footprint in the landscape definitely shined through.

Despite their small mundane appearances, the level of sophistication and sheer capabilities that our chips hold keep us excited. And the ways they make a difference in our lives will keep us going.

*Source: Cisco The Internet of Things: How the Next Evolution of the Internet Is Changing Everything, 2011

**Source: Cisco Global Cloud Index: Forecast and Methodology, 2013-2018, 2014