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		<title>EUV &#8211; Samsung Newsroom Malaysia</title>
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            <title>EUV &#8211; Samsung Newsroom Malaysia</title>
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				<title>Samsung Announces Industry’s First EUV DRAM with Shipment of First Million Modules</title>
				<link>https://news.samsung.com/my/samsung-announces-industrys-first-euv-dram-with-shipment-of-first-million-modules?utm_source=rss&amp;utm_medium=direct</link>
				<pubDate>Wed, 25 Mar 2020 10:55:52 +0000</pubDate>
						<category><![CDATA[Press Release]]></category>
		<category><![CDATA[Semiconductors]]></category>
		<category><![CDATA[10nm-class D1X DDR4]]></category>
		<category><![CDATA[EUV]]></category>
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									<description><![CDATA[Samsung Electronics, the world leader in advanced memory technology, today announced that it has successfully shipped one million of the industry’s]]></description>
																<content:encoded><![CDATA[<p>Samsung Electronics, the world leader in advanced memory technology, today announced that it has successfully shipped one million of the industry’s first<span> </span><span>10nm-class (D1x) </span>DDR4<span> </span><span>(Double Date Rate 4) </span>DRAM modules based on extreme ultraviolet (EUV) technology. The new EUV-based DRAM modules have completed global customer evaluations, and will open the door to more cutting-edge EUV process nodes for use in premium PC, mobile, enterprise server and datacenter applications.</p>
<p>&nbsp;</p>
<p>“With the production of our new<span> </span><span>EUV-based DRAM</span>, we are demonstrating our full commitment toward<span> </span><span>providing revolutionary DRAM solutions </span>in support of our global IT customers,” said Jung-bae Lee, executive vice president of DRAM Product &amp; Technology at Samsung Electronics. “This major advancement underscores how we will continue contributing to global IT innovation through timely development of leading-edge process technologies and next-generation memory products for the premium memory market.”</p>
<p>&nbsp;</p>
<p>Samsung is the first to adopt EUV in DRAM production to overcome<span> </span><span>challenges in DRAM scaling. </span>EUV technology reduces repetitive steps in multi-patterning and improves patterning accuracy, enabling enhanced performance and greater yields as well as shortened development time.</p>
<p>&nbsp;</p>
<p><span>EUV will be fully deployed in Samsung’s future generations of DRAM, starting with its </span>fourth-<span>generation 10nm-class (D1a) or the highly-advanced 14nm-class, DRAM. </span>Samsung expects to begin volume production of D1a-based DDR5 and LPDDR5 next year, which would double manufacturing productivity of the 12-inch D1x wafers.</p>
<p>&nbsp;</p>
<p>In line with the expansion of the DDR5/LPDDR5 market next year, the company will further strengthen its collaboration with leading IT customers and semiconductor vendors on optimizing standard specifications, as it accelerates the transition to DDR5/LPDDR5 throughout the memory market.</p>
<p>&nbsp;</p>
<p>To better address the growing demand for next-generation premium DRAM, Samsung will start the operation of a second semiconductor fabrication line in Pyeongtaek, South Korea, within the second half of this year.</p>
<p>&nbsp;</p>
<p>&nbsp;</p>
<h3><span><strong>Timeline of Samsung DRAM Milestones</strong></span></h3>
<table width="1000">
<tbody>
<tr>
<td width="300"><strong>Date</strong></td>
<td width="700"><strong>Samsung DRAM Milestones</strong></td>
</tr>
<tr>
<td width="141">2021 (TBD)</td>
<td width="384">4th-gen 10nm-class (1a) EUV-based 16Gb DDR5/LPDDR5 mass production</td>
</tr>
<tr>
<td width="141">March 2020</td>
<td width="384">4th-gen 10nm-class (1a) EUV-based DRAM development</td>
</tr>
<tr>
<td width="141">September 2019</td>
<td width="384">3rd-gen 10nm-class (1z) 8Gb DDR4 mass production</td>
</tr>
<tr>
<td width="141">June 2019</td>
<td width="384">2nd-gen 10nm-class (1y) 12Gb LPDDR5 mass production</td>
</tr>
<tr>
<td width="141">March 2019</td>
<td width="384">3rd-gen 10nm-class (1z) 8Gb DDR4 development</td>
</tr>
<tr>
<td width="141">November 2017</td>
<td width="384">2nd-gen 10nm-class (1y) 8Gb DDR4 mass production</td>
</tr>
<tr>
<td width="141">September 2016</td>
<td width="384">1st-gen 10nm-class (1x) 16Gb LPDDR4/4X mass production</td>
</tr>
<tr>
<td width="141">February 2016</td>
<td width="384">1st-gen 10nm-class (1x) 8Gb DDR4 mass production</td>
</tr>
<tr>
<td width="141">October 2015</td>
<td width="384">20nm (2z) 12Gb LPDDR4 mass production</td>
</tr>
<tr>
<td width="141">December 2014</td>
<td width="384">20nm (2z) 8Gb GDDR5 mass production</td>
</tr>
<tr>
<td width="141">December 2014</td>
<td width="384">20nm (2z) 8Gb LPDDR4 mass production</td>
</tr>
<tr>
<td width="141">October 2014</td>
<td width="384">20nm (2z) 8Gb DDR4 mass production</td>
</tr>
<tr>
<td width="141">February 2014</td>
<td width="384">20nm (2z) 4Gb DDR3 mass production</td>
</tr>
<tr>
<td width="141">February 2014</td>
<td width="384">20nm-class (2y) 8Gb LPDDR4 mass production</td>
</tr>
<tr>
<td width="141">November 2013</td>
<td width="384">20nm-class (2y) 6Gb LPDDR3 mass production</td>
</tr>
<tr>
<td width="141">November 2012</td>
<td width="384">20nm-class (2y) 4Gb DDR3 mass production</td>
</tr>
<tr>
<td width="141">September 2011</td>
<td width="384">20nm-class (2x) 2Gb DDR3 mass production</td>
</tr>
<tr>
<td width="141">July 2010</td>
<td width="384">30nm-class 2Gb DDR3 mass production</td>
</tr>
<tr>
<td width="141">February 2010</td>
<td width="384">40nm-class 4Gb DDR3 mass production</td>
</tr>
<tr>
<td width="141">July 2009</td>
<td width="384">40nm-class 2Gb DDR3 mass production</td>
</tr>
</tbody>
</table>
]]></content:encoded>
																				</item>
					<item>
				<title>[Editorial] 5nm: A Catalyst of the Fourth Industrial Revolution and What It Means for Semiconductor Innovations</title>
				<link>https://news.samsung.com/my/editorial-5nm-a-catalyst-of-the-fourth-industrial-revolution-and-what-it-means-for-semiconductor-innovations?utm_source=rss&amp;utm_medium=direct</link>
				<pubDate>Tue, 16 Apr 2019 17:36:07 +0000</pubDate>
						<category><![CDATA[Semiconductors]]></category>
		<category><![CDATA[5-nanometer]]></category>
		<category><![CDATA[5G]]></category>
		<category><![CDATA[5nm]]></category>
		<category><![CDATA[7LPP]]></category>
		<category><![CDATA[7nm Process]]></category>
		<category><![CDATA[AI]]></category>
		<category><![CDATA[EUV]]></category>
		<category><![CDATA[Robot]]></category>
		<category><![CDATA[S3 wafer fab]]></category>
		<category><![CDATA[SDB]]></category>
		<category><![CDATA[Semiconductor]]></category>
                <guid isPermaLink="false">http://bit.ly/2V6njg4</guid>
									<description><![CDATA[This week, Samsung Electronics announced that its 5-nanometer(nm) FinFET process technology based on EUV lithography  is now ready for production. This is a]]></description>
																<content:encoded><![CDATA[<p>This week, Samsung Electronics announced that its<span> </span><a href="https://news.samsung.com/global/samsung-successfully-completes-5nm-euv-development-to-allow-greater-area-scaling-and-ultra-low-power-benefits" target="_blank" rel="noopener">5-nanometer(nm) FinFET process technology based on EUV lithography</a>  is now ready for production. This is a remarkable accomplishment and testament to the capability of our colleagues at the S3 wafer fab in Hwaseong, Korea and their supply chain partners.</p>
<p>&nbsp;</p>
<p>For me, what is most exciting about this milestone is that it highlights how far the semiconductor industry innovations have come today and provides a glimpse into the evolutions that will shape the industry of tomorrow.</p>
<p>&nbsp;</p>
<p>Consider that the 5nm process is here in just six months after last October’s unveiling of the first commercial application of<span> </span><a href="https://news.samsung.com/global/samsung-electronics-starts-production-of-euv-based-7nm-lpp-process" target="_blank" rel="noopener">EUV in our 7nm process</a>. It’s a rapid progress made possible in large part by running thousands of wafer layers through EUV exposure systems each week. Hands-on experience is the only way to ascend the EUV learning curve, and that body of knowledge is growing daily.</p>
<p>&nbsp;</p>
<p>In the learning process, we’re seeing one of the biggest and broadest benefits of EUV – the simplification of design by moving away from increasingly complex multi-patterning lithography strategies. While still early, it’s increasingly clear that the reduced number of mask steps and more straightforward process is nothing short of a revolution for silicon designers. Sighs of relief will be heard as EUV will be seamlessly incorporated into the existing design architectures.</p>
<p>&nbsp;</p>
<p>Samsung’s 5nm is the next step in the evolution of EUV. 5nm will be more efficient and feature new innovations including Samsung’s proprietary Smart Diffusion Break (SDB) transistor architecture. One of the most important aspects of 5nm is that it supports 25 percent area reduction and 10 percent performance improvement or 20 percent power reduction than 7nm.</p>
<p>&nbsp;</p>
<p>Also, it will be largely design-rule compatible with the existing design of 7nm. Therefore, it is essentially a recharacterization of the technology, not redesign, which will substantially reduce time and the cost of implementation. This combination of technological advance and economic advantage is very much in line with a grand tradition of the semiconductor industry.</p>
<p>&nbsp;</p>
<p>This merging of technological advancement and economic benefits is very much in line with the grand tradition in the semiconductor industry as well as technologies including 5G, AI, Connected &amp; Automotive, Robot, etc. – constantly serving as a catalyst for the fourth industrial revolution, while simultaneously driving costs down. That’s why the evolution-moment of 5nm is, in its own unique way, as important as the innovation-moment of 7LPP.</p>
<p>&nbsp;</p>
<p>Bringing EUV into production has been a long, challenging process. It required substantial investment of time, money, and human resources. While there were certainly moments of doubt along the way, we had to pursue our vision. The 5nm announcement offers compelling evidence for the value of the investment. As businesses from diverse fields including Foundry, Fabless, the Design House, Packaging, Tests, etc., the semiconductor ecosystem will grow stronger. This is a new chapter for the semiconductor industry, and we are excited to be part of the continued journey in innovation.</p>
<p>&nbsp;</p>
<div id="attachment_7127" style="width: 410px" class="wp-caption aligncenter"><img class="size-full wp-image-7127" src="https://img.global.news.samsung.com/my/wp-content/uploads/2019/04/Daewon-Ha-Master_profilepic_highres.jpg" alt="" width="400" height="400" /><p class="wp-caption-text">Daewon Ha, Logic TD team, Semiconductor R&amp;D Center, Samsung Electronics</p></div>
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