So… About Samsung Mass Producing the Most Advanced 20nm DDR3 DRAM

on March 18, 2014
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Not so long ago, we shared the official press release on Samsung mass producing the industry’s most advanced 20nm DDR3 DRAM. It is pretty clear that the new 20nm 4Gb DDR3 DRAM made with Samsung’s exclusive technology is obviously highly advanced and innovative and this is not difficult to get a grasp of… but how did Samsung do it? According to the press release, there are two main technologies behind this: ‘modified double patterning’ and ‘ultrathin dielectric layers (atomic layer deposition)’. Umm, right. What in the world are they?

 

20nm 4Gb DDR3-04

 

First of all, ‘double patterning’ refers to the technology/process of engraving patterns of circuits on a wafer to ultimately build integrated circuits through photolithography. These patterns of circuits need to be engraved without damaging the transistors of each cell of the DRAM, because transistors charges and allows data in the capacitor to be read by the memory chip. Therefore, this process needs to be very precise and have complete uniformity. (Uniformity is a very important factor in DRAMs or any RAMs because they are so delicate that if even a small part of them is not precisely structured, they either won’t function or function ineffectively.) Remember we are talking about ‘Nano’ precise.

 

Taking the preceding 25nm DDR3 DRAM as an example, the ‘25nm’ represents the distance between transistors (which is much bigger than 25nm) of each cell. Therefore, a circuit is engraved between transistors of each cell with a measurement of 25nm utilizing the current immersion ArF lithography, the most standardize method of photolithography.

 

For a long time, it was thought that 25nm was the maximum capability of the immersion ArF lithography, not smaller. Therefore, many people thought it was nearly impossible to decrease it to 20nm with the current photolithography equipment. Even if it is capable of shooting lights in 20nm, because of the variation of the wavelength of the light, it would end up engraving the pattern of circuits 1~2nm deeper; which results in 22-24nm circuits. This is unacceptable for 4G DRAMs, if you want more than 4,000,000,000 cells to work perfect all the time in a high speed operating environment.

 

Samsung’s new technology has been able to modify the existing photolithography equipment so that it engraves it precisely at 20nm. Therefore the new 20nm 4G DDR3 can stably operate in high speed. Moreover, this technology has established the ground to quickly expand the production of the 20nm DRAM and the core technology for the next generation of 10nm-class DRAM production. Exciting!

 

Now let’s get into the ‘ultrathin dielectric layer’ of the 20nm DDR3 DRAM.

 

The capacitor is a part of DRAM’s cell that stores electric charges, which the electric charges inevitably leaks due to the characteristics of the DRAM. Here is something about the DRAM and its cells. The cell of the DRAM saves the electrical charges only for a very short amount of period in its capacitor. Therefore, the transistor needs to frequently refresh it with electricity. More specifically, it needs to refresh it every 64ms synchronizing with the CPU’s time clock. If there is even a single defected cell, the cell can ‘black out’ before it is refreshed, which causes the original data to be unreadable due to change in status of the electrical charges. Eventually, this results in defected RAM. Therefore, the dielectric layer, an electrical insulator, is applied thoroughly on the capacitor to prevent electric charges from leaking.

 

Conventionally, nanometer processing technology uses molecular sized material for dielectric layers. When dielectric layers are composed of a molecular sized material, the size of the particle is too big to establish layer uniformity. Moreover, to prevent something like electrons (smaller than a molecule) from leaking, the dielectric layers need to be either thicker or denser.

 

Why are the 20nm DDR3 DRAM’s dielectric layers ultrathin rather than ultra-thick?  Because the thicker the dielectric layers are, the fewer electrical charges are stored in the cell’s transistors; there is simply less room for them. Then how is it that Samsung 20nm DDR3 DRAM’s ultrathin layers are effective?

 

The material used in the 20nm DDR3 DRAM is measured in Angstrom (Å), a unit of length equal to 10−10 m, basically the size of an atom. The ultrathin dielectric layers of Samsung are composed of atomic materials, aka atomic layer deposition. This is why the amount of electric charges stored in the capacitor of the 20nm DDR DRAM doesn’t change much, in a significantly scale downed cell. Overall, the quality of the each cell of Samsung’s 20nm DDR DRAM is superior to the preceding 25nm DDR3 DRAM. Consequently, 20nm DDR3 DRAM’s superior cells enable high-speed operation, which is the most important characteristic of a DRAM, and low power consumption. Making the dielectric layers of the 20nm capacitor much denser and thinner than the 25nm capacitor was one of the keys to the successful development and now mass producing Samsung’s new 20nm 4G DDR3 .

 

Now going back to the very beginning, these two main technologies of the Samsung’s 20nm DDR3 DRAM are how Samsung has been able to continue scaling for more advanced DRAM. Now all we have to do is wait to enjoy the superior operating function of the new 20nm DDR3 DRAM.  

 

 

*All functionality features, specifications and other product information provided in this document including, but not limited to, the benefits, design, pricing, components, performance, availability, and capabilities of the product are subject to change without notice or obligation. 

 

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