[Editorial] Physics Busting at Its Seams

on April 9, 2015 by Inyoung Kim
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Physics Busting at Its Seams [Editorial]

 

Samsung’s Semiconductor Series Part 2

 

Read Part 1 

 

Semiconductors have been in a race to drive up both product performance and process manufacturing efficiency. Enter the mobile era, the market clamored for smaller and more powerful devices that would make the most out of their battery life. As the inside of such devices became prime real estate, components had to follow suit.

 

The convention was to shorten the distance between the circuitry. That means faster data transfers that require less energy, has more compact configurations and yet has the same capacity became possible. Fabrication productivity also got a boost as technology generations progressed.

 

While market needs catalyzed innovation and aggressive scaling in semiconductors, bringing digital experiences into the palms of our hands, chip fabrication methods quickly ran into a whole bunch of walls—or the lack of them. With details shrinking down to the billionth of a meter, it came to a point where traditional materials wouldn’t work anymore, electric charges started leaking and signals were getting crosstalk. In other words, scaling down the technology any further would gravely compromise the information being stored or waste the energy being consumed.

 

Our engineers couldn’t really defy the laws of physics. But they were able to bring about new designs and fabrication expertise in semiconductor technology that opened up meaningful opportunities for the industry.

 

▶ 14nm FinFET AP (application processor) – A warm and gooey marshmallow between two graham crackers is good enough as it is but if you make your s’more ‘denser,’ the crackers are brought closer together and the marshmallow gets squished up. That’s kind of what happened with the channel structures of transistors for FinFET. And no, the channel did not ooze out.

 

In February, we came out with the industry’s first mobile application processor (AP) based on advanced 14nm FinFET technology. By raising a ‘fin’ over the conducting channel and wrapping it over with the gate, the new structure addresses the problems of current leakage, or short-channel effect, that comes with finer technologies, while demonstrating greater power advantages and performance levels over our previous 20nm process technology. With our 14nm FinFET AP out in the hands of consumers, we’re staying busy prepping for 10nm FinFETs and beyond.

 

Read more: Samsung Announces Mass Production of Industry’s First 14nm FinFET Mobile Application Processor

 

▶ 20nm DRAM (Dynamic Random Access Memory) – For decades, the semiconductor industry had followed the pattern of doubling the density of ICs (integrated circuit) every two years. But delivering new technology refined enough for mass production got painstakingly harder. Due to limitations especially in the current technology of drawing crazy-thin lines, namely the lithography process, the 25nm design rule is where the industry thought to be the limit for DRAMs. It had been so for nearly two years. We were stuck.

 

Then, in 2014, came a breakthrough. Bleeding-edge methods such as modified double patterning and atomic layer deposition were introduced, heralding the arrival of the industry’s first 20nm DRAM. Contrary to common belief, we were able to utilize existing lithography tools, keeping costs viable as well. Not only was this a major breakthrough, but it also paves the way for sub-20nm nodes. We are currently the only manufacturer with this technology and are offering a full DRAM lineup for PC and enterprise systems as well as mobile device customers.

 

Read more: Samsung Electronics Starts Mass Production of Industry’s First 8-Gigabit Mobile DRAM

 

▶ 3D V-NAND (NAND flash memory) – Let’s say you have a single-story dormitory that you sectioned off for a number of occupants. You needed to accommodate more people, so rooms got smaller and the walls thinner. But tiny dorm rooms with thin walls are no fun at all. So what do you do? You build a skyscraper instead and give each of your tenants the entire floor, of course. All of a sudden, you don’t have to be fighting for space anymore and even better, everybody’s happy and much more productive. Voilà, 3D V-NAND flash memory.

 

Samsung is the first and still is the only company providing V-NAND products, which feature vertically stacked NAND flash cells. The technology marks a major milestone in memory technology as it overcomes the scaling limitations for conventional 2D planar structures, as well as drastically mitigating development time and resources. Even the first generation V-NAND demonstrated at least twice and up to ten times the reliability while also doubling its write performance. And don’t worry; a few dozen additional cell layers won’t affect the thickness of the final chip at all. Our second generation V-NAND products have also been very well received in the market, especially for applications in today’s SSDs that are equipped for the most demanding tasks.

 

Read more: Now I know my three-bit three-dee vee-nand ess-ess-dee [Editorial]

 

▶ ISOCELL (CMOS image sensors) – Between pixel size and image quality, there always was a delicate balance to maintain. A good image sensor will capture as much light, or photons, as possible, as accurately as possible through individual pixels within the sensor array. Theoretically, more pixels and larger sensor size would guarantee better picture qualities. However, we’re living in a mobile world. Since smaller pixel sizes come at the expense of the amount of light received, increasing the light sensitivity of each pixel has been the focus of image sensor development so far. Another problem with size; as pixels got packed closer together, photons that had been absorbed would wander into adjacent cells, making pictures blurry or diminishing color fidelity.

 

Introduced in 2014, our proprietary solution, ISOCELL, was to form a physical barrier between neighboring pixels so that more light is absorbed into the pixels correctly. This results in sharper and richer picture quality. The walls also create a wider chief ray angle (CRA) that reduces the height of the module. In other words, the pixels can afford to be less deep since they can capture those little photons hitting the pixel at a wider angle that would otherwise wander off to the pixel next door. All of these qualities make ISOCELL image sensors ideal for today’s compact devices.

 

Read more: Get the Big Picture: CMOS Image Sensors and ISOCELL

by Inyoung Kim

Manager at Device Solutions Division, Samsung Electronics

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